diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 4d6cb09..a7ff0d4 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -19,31 +19,6 @@ config TARGET_VE8313
 config TARGET_VME8349
 	bool "Support vme8349"
 
-config TARGET_MPC8308RDB
-	bool "Support MPC8308RDB"
-
-config TARGET_MPC8313ERDB
-	bool "Support MPC8313ERDB"
-	select SUPPORT_SPL
-
-config TARGET_MPC8315ERDB
-	bool "Support MPC8315ERDB"
-
-config TARGET_MPC8323ERDB
-	bool "Support MPC8323ERDB"
-
-config TARGET_MPC832XEMDS
-	bool "Support MPC832XEMDS"
-
-config TARGET_MPC8349EMDS
-	bool "Support MPC8349EMDS"
-
-config TARGET_MPC8349ITX
-	bool "Support MPC8349ITX"
-
-config TARGET_MPC837XEMDS
-	bool "Support MPC837XEMDS"
-
 config TARGET_MPC837XERDB
 	bool "Support MPC837XERDB"
 
@@ -68,14 +43,6 @@ config TARGET_HRCON
 endchoice
 
 source "board/esd/vme8349/Kconfig"
-source "board/freescale/mpc8308rdb/Kconfig"
-source "board/freescale/mpc8313erdb/Kconfig"
-source "board/freescale/mpc8315erdb/Kconfig"
-source "board/freescale/mpc8323erdb/Kconfig"
-source "board/freescale/mpc832xemds/Kconfig"
-source "board/freescale/mpc8349emds/Kconfig"
-source "board/freescale/mpc8349itx/Kconfig"
-source "board/freescale/mpc837xemds/Kconfig"
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/ids/ids8313/Kconfig"
 source "board/keymile/km83xx/Kconfig"
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 1eb3786..4313ac3 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -36,11 +36,7 @@ int pib_init(void)
 	i2c_write(0x26, 0x6, 1, &val8, 1);
 	val8 = 0x34;
 	i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_MPC832XEMDS)
-	val8 = 0xf9;            /* PMC2, PMC3 slot to PCI bus */
-#else
 	val8 = 0xf3;		/* PMC1, PMC2, PMC3 slot to PCI bus */
-#endif
 	i2c_write(0x26, 0x2, 1, &val8, 1);
 	val8 = 0xff;
 	i2c_write(0x26, 0x3, 1, &val8, 1);
@@ -55,12 +51,8 @@ int pib_init(void)
 
 	eieio();
 
-#if defined(CONFIG_MPC832XEMDS)
-	printf("PCI 32bit bus on PMC2 &PMC3\n");
-#else
 	printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
 #endif
-#endif
 
 #if defined(CONFIG_PQ_MDS_PIB_ATM)
 #if defined(CONFIG_MPC8569MDS)
@@ -76,24 +68,6 @@ int pib_init(void)
 	eieio();
 
 	printf("QOC3 ATM card on PMC0\n");
-#elif defined(CONFIG_MPC832XEMDS)
-	val8 = 0;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-	val8 = 0xf7;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x21, 0x6, 1, &val8, 1);
-	i2c_write(0x21, 0x7, 1, &val8, 1);
-
-	val8 = 0xdf;
-	i2c_write(0x21, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x21, 0x3, 1, &val8, 1);
-
-	eieio();
-
-	printf("QOC3 ATM card on PMC1\n");
 #endif
 #endif
 	/* Reset to original I2C bus */
diff --git a/board/freescale/mpc8308rdb/Kconfig b/board/freescale/mpc8308rdb/Kconfig
deleted file mode 100644
index 48d25e5..0000000
--- a/board/freescale/mpc8308rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8308RDB
-
-config SYS_BOARD
-	default "mpc8308rdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8308RDB"
-
-endif
diff --git a/board/freescale/mpc8308rdb/MAINTAINERS b/board/freescale/mpc8308rdb/MAINTAINERS
deleted file mode 100644
index 07ff2abd..0000000
--- a/board/freescale/mpc8308rdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8308RDB BOARD
-M:	Ilya Yanok <yanok@emcraft.com>
-S:	Maintained
-F:	board/freescale/mpc8308rdb/
-F:	include/configs/MPC8308RDB.h
-F:	configs/MPC8308RDB_defconfig
diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile
deleted file mode 100644
index ec2b85d..0000000
--- a/board/freescale/mpc8308rdb/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010
-# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8308rdb.o sdram.o
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
deleted file mode 100644
index 93e1c50..0000000
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <spi.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <fsl_esdhc.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-
-#define SPI_CS_MASK	0x00400000
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-	/* active low */
-	clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-	/* inactive high */
-	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-}
-#endif /* CONFIG_MPC8XXX_SPI */
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(bd_t *bd)
-{
-	return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-static u8 read_board_info(void)
-{
-	u8 val8;
-	i2c_set_bus_num(0);
-
-	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
-		return val8;
-	else
-		return 0;
-}
-
-int checkboard(void)
-{
-	static const char * const rev_str[] = {
-		"1.0",
-		"<reserved>",
-		"<reserved>",
-		"<reserved>",
-		"<unknown>",
-	};
-	u8 info;
-	int i;
-
-	info = read_board_info();
-	i = (!info) ? 4 : info & 0x03;
-
-	printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
-
-	return 0;
-}
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-	law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *pcie_reg[] = { pcie_regions_0 };
-
-	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
-					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(1, pcie_reg);
-}
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
-#ifdef CONFIG_MPC8XXX_SPI
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-
-	/*
-	 * Set proper bits in SICRH to allow SPI on header J8
-	 *
-	 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
-	 * switch. The pinmux configuration does not have a fine enough
-	 * granularity to support both simultaneously.
-	 */
-	clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
-	puts("WARNING: SPI enabled, TSEC2 support is broken\n");
-
-	/* Set header J8 SPI chip select output, disabled */
-	setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
-	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-#endif
-
-#ifdef CONFIG_VSC7385_IMAGE
-	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
-		CONFIG_VSC7385_IMAGE_SIZE)) {
-		puts("Failure uploading VSC7385 microcode.\n");
-		return 1;
-	}
-#endif
-
-	return 0;
-}
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
-	fdt_fixup_esdhc(blob, bd);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	int rv, num_if = 0;
-
-	/* Initialize TSECs first */
-	rv = cpu_eth_init(bis);
-	if (rv >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize TSECs.\n");
-
-	rv = pci_eth_init(bis);
-	if (rv >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize PCI Ethernet.\n");
-
-	return num_if;
-}
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
deleted file mode 100644
index 89b665e..0000000
--- a/board/freescale/mpc8308rdb/sdram.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
- *
- * Authors: Nick.Spence@freescale.com
- *          Wilson.Lo@freescale.com
- *          scottwood@freescale.com
- *
- * This files is  mostly identical to the original from
- * board\freescale\mpc8315erdb\sdram.c
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	out_be32(&im->sysconf.ddrlaw[0].bar,
-			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
-	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
-	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
-
-	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
-
-	/* Currently we use only one CS, so disable the other bank. */
-	out_be32(&im->ddr.cs_config[1], 0);
-
-	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
-	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
-	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-
-	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
-	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
-	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
-	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
-
-	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
-	sync();
-
-	/* enable DDR controller */
-	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
-	sync();
-
-	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
-}
-
-phys_size_t initdram(int board_type)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize;
-
-	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM */
-	msize = fixed_sdram();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}
diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig
deleted file mode 100644
index 145608f..0000000
--- a/board/freescale/mpc8313erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8313ERDB
-
-config SYS_BOARD
-	default "mpc8313erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8313ERDB"
-
-endif
diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS
deleted file mode 100644
index 807fb0b..0000000
--- a/board/freescale/mpc8313erdb/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MPC8313ERDB BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc8313erdb/
-F:	include/configs/MPC8313ERDB.h
-F:	configs/MPC8313ERDB_33_defconfig
-F:	configs/MPC8313ERDB_66_defconfig
-F:	configs/MPC8313ERDB_NAND_33_defconfig
-F:	configs/MPC8313ERDB_NAND_66_defconfig
diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile
deleted file mode 100644
index 77fad75..0000000
--- a/board/freescale/mpc8313erdb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8313erdb.o sdram.o
diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README
deleted file mode 100644
index be7ef32..0000000
--- a/board/freescale/mpc8313erdb/README
+++ /dev/null
@@ -1,111 +0,0 @@
-Freescale MPC8313ERDB Board
------------------------------------------
-
-1.	Board Switches and Jumpers
-
-	S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
-	To boot the image at 0xFE000000 in NOR flash, use these DIP
-	switch settings for S3 S4:
-
-	+------+	+------+
-	|      |	| **** |
-	| **** |	|      |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	To boot the image at the beginning of NAND flash, use these
-	DIP switch settings for S3 S4:
-
-	+------+	+------+
-	| *    |	|  *** |
-	|  *** |	| *    |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x07ff_ffff	DDR		 128M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xe200_0000	0xe20f_ffff	PCI IO		 16M
-	0xe280_0000	0xe280_7fff	NAND FLASH (CS1) 32K
-	0xf000_0000	0xf001_ffff	VSC7385 (CS2)	 128K
-	0xfa00_0000	0xfa00_7fff	Board Status/	 32K
-					LED Control (CS3)
-	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
-
-	When booting from NAND, NAND flash is CS0 and NOR flash
-	is CS1.
-
-3.	Definitions
-
-3.1	Explanation of NEW definitions in:
-
-	include/configs/MPC8313ERDB.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC831x		MPC831x specific
-	CONFIG_MPC8313ERDB	MPC8313ERDB board specific
-
-4.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8313ERDB_XXX_config
-	(where XXX is:
-	   33 - 33 MHz oscillator, boot from NOR flash
-	   66 - 66 MHz oscillator, boot from NOR flash
-	   NAND_33 - 33 MHz oscillator, boot from NAND flash
-	   NAND_66 - 66 MHz oscillator, boot from NAND flash)
-	make
-
-5.	Downloading and Flashing Images
-
-5.1	Reflash U-boot Image using U-boot
-
-	NOR flash:
-
-	=>run tftpflash
-
-	You may want to try
-	=>tftpboot $loadaddr $uboot
-	first, to make sure that the TFTP load will succeed before it
-	goes ahead and wipes out your current firmware.  And of course,
-	have an alternate means of programming the flash available
-	if the new u-boot doesn't boot.
-
-	NAND flash:
-
-	=>tftpboot $loadaddr <filename>
-	=>nand erase 0 0x80000
-	=>nand write $loadaddr 0 0x80000
-
-	...where 0x80000 is the filesize rounded up to
-	the next 0x20000 increment.
-
-5.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	=>run nfsboot
-	or
-	=>run ramboot
-
-6	Notes
-
-	The console baudrate for MPC8313ERDB is 115200bps.
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
deleted file mode 100644
index eac193e..0000000
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Author: Scott Wood <scottwood@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <pci.h>
-#include <mpc83xx.h>
-#include <vsc7385.h>
-#include <ns16550.h>
-#include <nand.h>
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-#include <asm/gpio.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-#endif
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-	mpc83xx_gpio_init_f();
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-	mpc83xx_gpio_init_r();
-#endif
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8313ERDB\n");
-	return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static struct pci_region pci_regions[] = {
-	{
-		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
-		.size = CONFIG_SYS_PCI1_MEM_SIZE,
-		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
-		.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
-		.size = CONFIG_SYS_PCI1_MMIO_SIZE,
-		.flags = PCI_REGION_MEM
-	},
-	{
-		.bus_start = CONFIG_SYS_PCI1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
-		.size = CONFIG_SYS_PCI1_IO_SIZE,
-		.flags = PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci_regions };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-}
-
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
-	int rc = 0;
-
-#ifdef CONFIG_VSC7385_IMAGE
-	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
-		CONFIG_VSC7385_IMAGE_SIZE)) {
-		puts("Failure uploading VSC7385 microcode.\n");
-		rc = 1;
-	}
-#endif
-
-	return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
-#else /* CONFIG_SPL_BUILD */
-void board_init_f(ulong bootflag)
-{
-	board_early_init_f();
-	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
-		      CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (gd->flags & GD_FLG_SILENT)
-		return;
-
-	if (c == '\n')
-		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
-	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
deleted file mode 100644
index 6282c3d..0000000
--- a/board/freescale/mpc8313erdb/sdram.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Authors: Nick.Spence@freescale.com
- *          Wilson.Lo@freescale.com
- *          scottwood@freescale.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-#endif
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	__udelay(50000);
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[0].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
-			CSBNDS_EA);
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Currently we use only one CS, so disable the other bank. */
-	im->ddr.cs_config[1] = 0;
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
-	else
-#endif
-		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
-
-	im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	sync();
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-#endif
-
-	return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &im->im_lbc;
-	u32 msize;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	msize = fixed_sdram();
-
-	/* Local Bus setup lbcr and mrtpr */
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	sync();
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-#endif
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}
diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig
deleted file mode 100644
index f76b0d1..0000000
--- a/board/freescale/mpc8315erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8315ERDB
-
-config SYS_BOARD
-	default "mpc8315erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8315ERDB"
-
-endif
diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
deleted file mode 100644
index 938c152..0000000
--- a/board/freescale/mpc8315erdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8315ERDB BOARD
-M:	Dave Liu <daveliu@freescale.com>
-S:	Maintained
-F:	board/freescale/mpc8315erdb/
-F:	include/configs/MPC8315ERDB.h
-F:	configs/MPC8315ERDB_defconfig
diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile
deleted file mode 100644
index fbb68c5..0000000
--- a/board/freescale/mpc8315erdb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8315erdb.o sdram.o
diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README
deleted file mode 100644
index b32132d..0000000
--- a/board/freescale/mpc8315erdb/README
+++ /dev/null
@@ -1,105 +0,0 @@
-Freescale MPC8315ERDB Board
------------------------------------------
-
-1.	Board Switches and Jumpers
-
-	S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
-	To boot the image at 0xFE000000 in NOR flash, use these DIP
-	switch settings for S3 S4:
-
-	+------+	+------+
-	|      |	| **** |
-	| **** |	|      |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	To boot the image at the beginning of NAND flash, use these
-	DIP switch settings for S3 S4:
-
-	+------+	+------+
-	| *    |	|  *** |
-	|  *** |	| *    |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x07ff_ffff	DDR		 128M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xe030_0000	0xe03f_ffff	PCI IO		 1M
-	0xe060_0000	0xe060_7fff	NAND FLASH (CS1) 32K
-	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
-
-	When booting from NAND, NAND flash is CS0 and NOR flash
-	is CS1.
-
-3.	Definitions
-
-3.1	Explanation of NEW definitions in:
-
-	include/configs/MPC8315ERDB.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC831x		MPC831x specific
-	CONFIG_MPC8315		MPC8315 specific
-	CONFIG_MPC8315ERDB	MPC8315ERDB board specific
-
-4.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
-	make all
-
-5.	Downloading and Flashing Images
-
-5.1	Reflash U-boot Image using U-boot
-
-	NOR flash:
-
-	tftp 40000 u-boot.bin
-	protect off all
-	erase fe000000 fe1fffff
-
-	cp.b 40000 fe000000 xxxx
-	protect on all
-
-	You have to supply the correct byte count with 'xxxx'
-	from the TFTP result log.
-
-	NAND flash:
-
-	=>tftpboot $loadaddr <filename>
-	=>nand erase 0 0x80000
-	=>nand write $loadaddr 0 0x80000
-
-	...where 0x80000 is the filesize rounded up to
-	the next 0x20000 increment.
-
-5.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	=>run nfsboot
-	or
-	=>run ramboot
-
-6	Notes
-
-	The console baudrate for MPC8315ERDB is 115200bps.
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
deleted file mode 100644
index ed611c5..0000000
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Author: Scott Wood <scottwood@freescale.com>
- *         Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-
-#ifndef CONFIG_NAND_SPL
-
-static u8 read_board_info(void)
-{
-	u8 val8;
-	i2c_set_bus_num(0);
-
-	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
-		return val8;
-	else
-		return 0;
-}
-
-int checkboard(void)
-{
-	static const char * const rev_str[] = {
-		"0.0",
-		"0.1",
-		"1.0",
-		"1.1",
-		"<unknown>",
-	};
-	u8 info;
-	int i;
-
-	info = read_board_info();
-	i = (!info) ? 4: info & 0x03;
-
-	printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
-
-	return 0;
-}
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
-		size: CONFIG_SYS_PCI_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
-		size: CONFIG_SYS_PCI_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_IO_BASE,
-		phys_start: CONFIG_SYS_PCI_IO_PHYS,
-		size: CONFIG_SYS_PCI_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure the clock for PCIE controller */
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
-				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(2, pcie_reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_tsec1_fixup(void *fdt, bd_t *bd)
-{
-	const char disabled[] = "disabled";
-	const char *path;
-	int ret;
-
-	if (hwconfig_arg_cmp("board_type", "tsec1")) {
-		return;
-	} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
-		printf("NOTICE: No or unknown board_type hwconfig specified.\n"
-		       "        Assuming board with TSEC1.\n");
-		return;
-	}
-
-	ret = fdt_path_offset(fdt, "/aliases");
-	if (ret < 0) {
-		printf("WARNING: can't find /aliases node\n");
-		return;
-	}
-
-	path = fdt_getprop(fdt, ret, "ethernet0", NULL);
-	if (!path) {
-		printf("WARNING: can't find ethernet0 alias\n");
-		return;
-	}
-
-	do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	fdt_fixup_dr_usb(blob, bd);
-	fdt_tsec1_fixup(blob, bd);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis);	/* Initialize TSECs first */
-	return pci_eth_init(bis);
-}
-
-#else /* CONFIG_NAND_SPL */
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8315ERDB\n");
-	return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
-	board_early_init_f();
-	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
-		      CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (gd->flags & GD_FLG_SILENT)
-		return;
-
-	if (c == '\n')
-		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
-	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-
-#endif /* CONFIG_NAND_SPL */
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
deleted file mode 100644
index 6c94312..0000000
--- a/board/freescale/mpc8315erdb/sdram.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Authors: Nick.Spence@freescale.com
- *          Wilson.Lo@freescale.com
- *          scottwood@freescale.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-#ifndef CONFIG_SYS_RAMBOOT
-static long fixed_sdram(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	__udelay(50000);
-
-	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Currently we use only one CS, so disable the other bank. */
-	im->ddr.cs_config[1] = 0;
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
-	else
-		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	sync();
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	sync();
-
-	return msize;
-}
-#else
-static long fixed_sdram(void)
-{
-	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM */
-	msize = fixed_sdram();
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}
diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig
deleted file mode 100644
index acf8122..0000000
--- a/board/freescale/mpc8323erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8323ERDB
-
-config SYS_BOARD
-	default "mpc8323erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8323ERDB"
-
-endif
diff --git a/board/freescale/mpc8323erdb/MAINTAINERS b/board/freescale/mpc8323erdb/MAINTAINERS
deleted file mode 100644
index 05057c0..0000000
--- a/board/freescale/mpc8323erdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8323ERDB BOARD
-M:	Michael Barkowski <michael.barkowski@freescale.com>
-S:	Maintained
-F:	board/freescale/mpc8323erdb/
-F:	include/configs/MPC8323ERDB.h
-F:	configs/MPC8323ERDB_defconfig
diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile
deleted file mode 100644
index f2e7497..0000000
--- a/board/freescale/mpc8323erdb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8323erdb.o
diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README
deleted file mode 100644
index 6f89829..0000000
--- a/board/freescale/mpc8323erdb/README
+++ /dev/null
@@ -1,71 +0,0 @@
-Freescale MPC8323ERDB Board
------------------------------------------
-
-1.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x03ff_ffff	DDR		 64M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xd000_0000	0xd3ff_ffff	PCI IO		 64M
-	0xfe00_0000	0xfeff_ffff	NOR FLASH (CS0)	 16M
-
-2.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8323ERDB_config
-	make
-
-3.	Downloading and Flashing Images
-
-3.1	Reflash U-boot Image using U-boot
-
-	N.b, have an alternate means of programming
-	the flash available if the new u-boot doesn't boot.
-
-	First try a:
-
-	tftpboot $loadaddr $uboot
-
-	to make sure that the TFTP load will succeed before
-	an erase goes ahead and wipes out your current firmware.
-	Then do a:
-
-	run tftpflash
-
-	which is a shorter version of the manual sequence:
-
-	tftp $loadaddr u-boot.bin
-	protect off fe000000 +$filesize
-	erase fe000000 +$filesize
-	cp.b $loadaddr fe000000 $filesize
-
-	To keep your old u-boot's environment variables, do a:
-
-	saveenv
-
-	prior to resetting the board.
-
-3.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	run nfsboot
-
-	or
-
-	run ramboot
-
-4	Notes
-
-	The console baudrate for MPC8323ERDB is 115200bps.
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
deleted file mode 100644
index 0a0152a..0000000
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Michael Barkowski <michael.barkowski@freescale.com>
- * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#include <libfdt.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/mmu.h>
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* UCC3 */
-	{1,  0, 1, 0, 1}, /* TxD0 */
-	{1,  1, 1, 0, 1}, /* TxD1 */
-	{1,  2, 1, 0, 1}, /* TxD2 */
-	{1,  3, 1, 0, 1}, /* TxD3 */
-	{1,  9, 1, 0, 1}, /* TxER */
-	{1, 12, 1, 0, 1}, /* TxEN */
-	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
-	{1,  4, 2, 0, 1}, /* RxD0 */
-	{1,  5, 2, 0, 1}, /* RxD1 */
-	{1,  6, 2, 0, 1}, /* RxD2 */
-	{1,  7, 2, 0, 1}, /* RxD3 */
-	{1,  8, 2, 0, 1}, /* RxER */
-	{1, 10, 2, 0, 1}, /* RxDV */
-	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
-	{1, 11, 2, 0, 1}, /* COL */
-	{1, 13, 2, 0, 1}, /* CRS */
-
-	/* UCC2 */
-	{0, 18, 1, 0, 1}, /* TxD0 */
-	{0, 19, 1, 0, 1}, /* TxD1 */
-	{0, 20, 1, 0, 1}, /* TxD2 */
-	{0, 21, 1, 0, 1}, /* TxD3 */
-	{0, 27, 1, 0, 1}, /* TxER */
-	{0, 30, 1, 0, 1}, /* TxEN */
-	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
-
-	{0, 22, 2, 0, 1}, /* RxD0 */
-	{0, 23, 2, 0, 1}, /* RxD1 */
-	{0, 24, 2, 0, 1}, /* RxD2 */
-	{0, 25, 2, 0, 1}, /* RxD3 */
-	{0, 26, 1, 0, 1}, /* RxER */
-	{0, 28, 2, 0, 1}, /* Rx_DV */
-	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
-	{0, 29, 2, 0, 1}, /* COL */
-	{0, 31, 2, 0, 1}, /* CRS */
-
-	{3,  4, 3, 0, 2}, /* MDIO */
-	{3,  5, 1, 0, 2}, /* MDC */
-
-	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-
-	msize = fixed_sdram();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__ ("sync");
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	__asm__ __volatile__ ("sync");
-	return msize;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8323ERDB\n");
-	return 0;
-}
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci_regions };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
-int mac_read_from_eeprom(void)
-{
-	uchar buf[28];
-	char str[18];
-	int i = 0;
-	unsigned int crc = 0;
-	unsigned char enetvar[32];
-
-	/* Read MAC addresses from EEPROM */
-	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
-		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR);
-	} else {
-		uint32_t crc_buf;
-
-		memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
-
-		if (crc32(crc, buf, 24) == crc_buf) {
-			printf("Reading MAC from EEPROM\n");
-			for (i = 0; i < 4; i++) {
-				if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
-					sprintf(str,
-						"%02X:%02X:%02X:%02X:%02X:%02X",
-						buf[i * 6], buf[i * 6 + 1],
-						buf[i * 6 + 2], buf[i * 6 + 3],
-						buf[i * 6 + 4], buf[i * 6 + 5]);
-					sprintf((char *)enetvar,
-						i ? "eth%daddr" : "ethaddr", i);
-					setenv((char *)enetvar, str);
-				}
-			}
-		}
-	}
-	return 0;
-}
-#endif				/* CONFIG_I2C_MAC_OFFSET */
diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig
deleted file mode 100644
index e4cfa15..0000000
--- a/board/freescale/mpc832xemds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC832XEMDS
-
-config SYS_BOARD
-	default "mpc832xemds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC832XEMDS"
-
-endif
diff --git a/board/freescale/mpc832xemds/MAINTAINERS b/board/freescale/mpc832xemds/MAINTAINERS
deleted file mode 100644
index 56d7073..0000000
--- a/board/freescale/mpc832xemds/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-MPC832XEMDS BOARD
-M:	Dave Liu <daveliu@freescale.com>
-S:	Maintained
-F:	board/freescale/mpc832xemds/
-F:	include/configs/MPC832XEMDS.h
-F:	configs/MPC832XEMDS_defconfig
-F:	configs/MPC832XEMDS_ATM_defconfig
-F:	configs/MPC832XEMDS_HOST_33_defconfig
-F:	configs/MPC832XEMDS_HOST_66_defconfig
-F:	configs/MPC832XEMDS_SLAVE_defconfig
diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile
deleted file mode 100644
index 6676351..0000000
--- a/board/freescale/mpc832xemds/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc832xemds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README
deleted file mode 100644
index 4142aa9..0000000
--- a/board/freescale/mpc832xemds/README
+++ /dev/null
@@ -1,128 +0,0 @@
-Freescale MPC832XEMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
-	For some reason, the HW designers describe the switch settings
-	in terms of 0 and 1, and then map that to physical switches where
-	the label "On" refers to logic 0 and "Off" is logic 1.
-
-	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
-	bits may contribute to signals that are numbered based at 0,
-	and some of those signals may be high-bit-number-0 too.  Heed
-	well the names and labels and do not get confused.
-
-		"Off" == 1
-		"On"  == 0
-
-	SW3 is switch 18 as silk-screened onto the board.
-	SW4[8] is the bit labeled 8 on Switch 4.
-	SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
-	SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
-	SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
-		and bits labeled 8 is set as "Off".
-
-1.1 For the MPC832XEMDS PROTO Board
-
-	First, make sure the board default setting is consistent with the document
-		 shipped with your board. Then apply the following setting:
-	SW3[1-8]= 0000_1000  (core PLL setting, core enable)
-	SW4[1-8]= 0001_0010  (Flash boot on local bus, system PLL setting)
-	SW5[1-8]= 0010_0110  (Boot from high end)
-	SW6[1-8]= 0011_0100  (Flash boot on 16 bit local bus)
-	SW7[1-8]= 1000_0011  (QE PLL setting)
-
-	ENET3/4 MII mode settings:
-	J1 1-2 (ETH3_TXER)
-	J2 2-3 (MII mode)
-	J3 2-3 (MII mode)
-	J4 2-3 (ADSL clockOscillator)
-	J5 1-2 (ETH4_TXER)
-	J6 2-3 (ClockOscillator)
-	JP1 removed (don't force PORESET)
-	JP2 mounted (ETH4/2 MII)
-	JP3 mounted (ETH3 MII)
-	JP4 mounted (HRCW from BCSR)
-
-	ENET3/4 RMII mode settings:
-	J1 1-2 (ETH3_TXER)
-	J2 1-2 (RMII mode)
-	J3 1-2 (RMII mode)
-	J4 2-3 (ADSL clockOscillator)
-	J5 1-2 (ETH4_TXER)
-	J6 2-3 (ClockOscillator)
-	JP1 removed (don't force PORESET)
-	JP2 removed (ETH4/2 RMII)
-	JP3 removed (ETH3 RMII)
-	JP4 removed (HRCW from FLASH)
-
-	on board Oscillator: 66M
-
-
-2. Memory Map
-
-2.1 The memory map should look pretty much like this:
-
-	0x0000_0000	0x7fff_ffff	DDR			2G
-	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
-	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
-	0xc000_0000	0xdfff_ffff	Empty			512M
-	0xe000_0000	0xe01f_ffff	Int Mem Reg Space	2M
-	0xe020_0000	0xe02f_ffff	Empty			1M
-	0xe030_0000	0xe03f_ffff	PCI IO			1M
-	0xe040_0000	0xefff_ffff	Empty			252M
-	0xf400_0000	0xf7ff_ffff	Empty			64M
-	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
-	0xf800_8000	0xf800_ffff	PIB CS2			32K
-	0xf801_0000	0xf801_7fff	PIB CS3			32K
-	0xfe00_0000	0xfeff_ffff	FLASH on CS0		16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
-	include/configs/MPC832XEPB.h
-
-    CONFIG_MPC83xx	MPC83xx family for MPC8349, MPC8360 and MPC832x
-    CONFIG_MPC832x	MPC832x specific
-    CONFIG_MPC832XEMDS	MPC832XEMDS board specific
-
-4. Compilation
-
-	Assuming you're using BASH shell:
-
-		export CROSS_COMPILE=your-cross-compile-prefix
-		cd u-boot
-		make distclean
-		make MPC832XEMDS_config
-		make
-
-	MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
-
-		1)Make sure the DIP SW support PCI mode as described in Section 1.1.
-
-		2)To Make U-Boot image support PCI 33MHz, use
-			Make MPC832XEMDS_HOST_33_config
-
-		3)To Make U-Boot image support PCI 66MHz, use
-			Make MPC832XEMDS_HOST_66M_config
-
-5. Downloading and Flashing Images
-
-5.0 Download over network:
-
-	tftp 10000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
-	tftp 20000 u-boot.bin
-	protect off fe000000 fe0fffff
-	erase fe000000 fe0fffff
-	cp.b 20000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
-	1) The console baudrate for MPC832XEMDS is 115200bps.
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
deleted file mode 100644
index adf4254..0000000
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* ETH3 */
-	{1,  0, 1, 0, 1}, /* TxD0 */
-	{1,  1, 1, 0, 1}, /* TxD1 */
-	{1,  2, 1, 0, 1}, /* TxD2 */
-	{1,  3, 1, 0, 1}, /* TxD3 */
-	{1,  9, 1, 0, 1}, /* TxER */
-	{1, 12, 1, 0, 1}, /* TxEN */
-	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
-	{1,  4, 2, 0, 1}, /* RxD0 */
-	{1,  5, 2, 0, 1}, /* RxD1 */
-	{1,  6, 2, 0, 1}, /* RxD2 */
-	{1,  7, 2, 0, 1}, /* RxD3 */
-	{1,  8, 2, 0, 1}, /* RxER */
-	{1, 10, 2, 0, 1}, /* RxDV */
-	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
-	{1, 11, 2, 0, 1}, /* COL */
-	{1, 13, 2, 0, 1}, /* CRS */
-
-	/* ETH4 */
-	{1, 18, 1, 0, 1}, /* TxD0 */
-	{1, 19, 1, 0, 1}, /* TxD1 */
-	{1, 20, 1, 0, 1}, /* TxD2 */
-	{1, 21, 1, 0, 1}, /* TxD3 */
-	{1, 27, 1, 0, 1}, /* TxER */
-	{1, 30, 1, 0, 1}, /* TxEN */
-	{3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
-
-	{1, 22, 2, 0, 1}, /* RxD0 */
-	{1, 23, 2, 0, 1}, /* RxD1 */
-	{1, 24, 2, 0, 1}, /* RxD2 */
-	{1, 25, 2, 0, 1}, /* RxD3 */
-	{1, 26, 1, 0, 1}, /* RxER */
-	{1, 28, 2, 0, 1}, /* Rx_DV */
-	{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
-	{1, 29, 2, 0, 1}, /* COL */
-	{1, 31, 2, 0, 1}, /* CRS */
-
-	{3,  4, 3, 0, 2}, /* MDIO */
-	{3,  5, 1, 0, 2}, /* MDC */
-
-	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int board_early_init_f(void)
-{
-	volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
-
-	/* Enable flash write */
-	bcsr[9] &= ~0x08;
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
-	pib_init();
-#endif
-	return 0;
-}
-
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-
-	msize = fixed_sdram();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1) {
-			return -1;
-		}
-	}
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 128)
-#warning Currenly any ddr size other than 128 is not supported
-#endif
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__ ("sync");
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	__asm__ __volatile__ ("sync");
-	return msize;
-}
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC832XEMDS\n");
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
deleted file mode 100644
index e8b2b11..0000000
--- a/board/freescale/mpc832xemds/pci.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include "../common/pq-mds-pib.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
-		size: CONFIG_SYS_PCI2_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_IO_BASE,
-		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
-		size: CONFIG_SYS_PCI2_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
-		size: CONFIG_SYS_PCI2_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	mpc83xx_pci_init(1, reg);
-
-	/*
-	 * Configure PCI Inbound Translation Windows
-	 */
-	pci_ctrl[0].pitar0 = 0x0;
-	pci_ctrl[0].pibar0 = 0x0;
-	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
-	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
-	pci_ctrl[0].pitar1 = 0x0;
-	pci_ctrl[0].pibar1 = 0x0;
-	pci_ctrl[0].piebar1 = 0x0;
-	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
-	pci_ctrl[0].pitar2 = 0x0;
-	pci_ctrl[0].pibar2 = 0x0;
-	pci_ctrl[0].piebar2 = 0x0;
-	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
-	/* Unlock the configuration bit */
-	mpc83xx_pcislave_unlock(0);
-	printf("PCI:   Agent mode enabled\n");
-}
-#else
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
-	/* initialize the PCA9555PW IO expander on the PIB board */
-	pib_init();
-
-#if defined(CONFIG_PCI_66M)
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
-	printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
-	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
-	printf("PCI clock is 33MHz\n");
-#else
-	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
-	printf("PCI clock is 66MHz\n");
-#endif
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif				/* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig
deleted file mode 100644
index 51f0b34..0000000
--- a/board/freescale/mpc8349emds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8349EMDS
-
-config SYS_BOARD
-	default "mpc8349emds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8349EMDS"
-
-endif
diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS
deleted file mode 100644
index 141e77a..0000000
--- a/board/freescale/mpc8349emds/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8349EMDS BOARD
-M:	Kim Phillips <kim.phillips@freescale.com>
-S:	Maintained
-F:	board/freescale/mpc8349emds/
-F:	include/configs/MPC8349EMDS.h
-F:	configs/MPC8349EMDS_defconfig
diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile
deleted file mode 100644
index 5c315f9..0000000
--- a/board/freescale/mpc8349emds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc8349emds.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
deleted file mode 100644
index aae003d..0000000
--- a/board/freescale/mpc8349emds/ddr.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{2,  300,    4,   4,    2,  0},
-	{2,  365,    4,   6,    2,  0},
-	{2,  450,    4,   7,    2,  0},
-	{2,  850,    4,  31,    2,  0},
-	{1,  300,    4,   4,    2,  0},
-	{1,  365,    4,   6,    2,  0},
-	{1,  450,    4,   7,    2,  0},
-	{1,  850,    4,  31,    2,  0},
-	{}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	unsigned int i;
-	ulong ddr_freq;
-
-	if (ctrl_num != 0)	/* we have only one controller */
-		return;
-	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-		if (pdimm[i].n_ranks)
-			break;
-	}
-	if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)	/* no DIMM */
-		return;
-
-	pbsp = udimm0;
-
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks ==  pdimm[i].n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->twot_en = pbsp_highest->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-found:
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	popts->dqs_config = 0;	/* only true DQS signal is used on board */
-}
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
deleted file mode 100644
index 02b5040..0000000
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <spi.h>
-#include <miiphy.h>
-#ifdef CONFIG_SYS_FSL_DDR2
-#include <fsl_ddr_sdram.h>
-#else
-#include <spd_sdram.h>
-#endif
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-int fixed_sdram(void);
-void sdram_init(void);
-
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-int board_early_init_f (void)
-{
-	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
-
-	/* Enable flash write */
-	bcsr[1] &= ~0x01;
-
-#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
-	/* Use USB PHY on SYS board */
-	bcsr[5] |= 0x02;
-#endif
-
-	return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	phys_size_t msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_SYS_FSL_DDR2
-	msize = spd_sdram() * 1024 * 1024;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	ddr_enable_ecc(msize);
-#endif
-#else
-	msize = fsl_ddr_sdram();
-#endif
-#else
-	msize = fixed_sdram() * 1024 * 1024;
-#endif
-	/*
-	 * Initialize SDRAM if it is on local bus.
-	 */
-	sdram_init();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE;
-	u32 ddr_size = msize << 20;	/* DDR size in bytes */
-	u32 ddr_size_log2 = __ilog2(ddr_size);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-#ifdef CONFIG_DDR_II
-	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[2].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
-				CSBNDS_EA_SHIFT) & CSBNDS_EA);
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-
-	/* currently we use only one CS, so disable the other banks */
-	im->ddr.cs_config[0] = 0;
-	im->ddr.cs_config[1] = 0;
-	im->ddr.cs_config[3] = 0;
-
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
-	im->ddr.sdram_cfg =
-		SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
-		| SDRAM_CFG_2T_EN
-#endif
-		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
-#if defined (CONFIG_DDR_32BIT)
-	/* for 32-bit mode burst length is 8 */
-	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
-	udelay(200);
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	return msize;
-}
-#endif/*!CONFIG_SYS_SPD_EEPROM*/
-
-
-int checkboard (void)
-{
-	/*
-	 * Warning: do not read the BCSR registers here
-	 *
-	 * There is a timing bug in the 8349E and 8349EA BCSR code
-	 * version 1.2 (read from BCSR 11) that will cause the CFI
-	 * flash initialization code to overwrite BCSR 0, disabling
-	 * the serial ports and gigabit ethernet
-	 */
-
-	puts("Board: Freescale MPC8349EMDS\n");
-	return 0;
-}
-
-/*
- * if MPC8349EMDS is soldered with SDRAM
- */
-#if defined(CONFIG_SYS_BR2_PRELIM)  \
-	&& defined(CONFIG_SYS_OR2_PRELIM) \
-	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
-	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void sdram_init(void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &immap->im_lbc;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
-	/*
-	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
-	 */
-
-	/* setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	asm("sync");
-
-	/*
-	 * Configure the SDRAM controller Machine Mode Register.
-	 */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
-	asm("sync");
-	/*1 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*2 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*3 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*4 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*5 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*6 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*7 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*8 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	/* 0x58636733; mode register write operation */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-}
-#else
-void sdram_init(void)
-{
-}
-#endif
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-
-#define SPI_CS_MASK	0x80000000
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat &= ~SPI_CS_MASK;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat |=  SPI_CS_MASK;
-}
-#endif /* CONFIG_HARD_SPI */
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
deleted file mode 100644
index 9f7324f..0000000
--- a/board/freescale/mpc8349emds/pci.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
-		size: CONFIG_SYS_PCI2_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_IO_BASE,
-		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
-		size: CONFIG_SYS_PCI2_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
-		size: CONFIG_SYS_PCI2_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-#endif
-
-#ifndef CONFIG_PCISLAVE
-void pib_init(void)
-{
-	u8 val8, orig_i2c_bus;
-	/*
-	 * Assign PIB PMC slot to desired PCI bus
-	 */
-	/* Switch temporarily to I2C bus #2 */
-	orig_i2c_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	val8 = 0;
-	i2c_write(0x23, 0x6, 1, &val8, 1);
-	i2c_write(0x23, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x23, 0x2, 1, &val8, 1);
-	i2c_write(0x23, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x26, 0x6, 1, &val8, 1);
-	val8 = 0x34;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(PCI_64BIT)
-	val8 = 0xf4;	/* PMC2:PCI1/64-bit */
-#elif defined(PCI_ALL_PCI1)
-	val8 = 0xf3;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
-#elif defined(PCI_ONE_PCI1)
-	val8 = 0xf9;	/* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
-#else
-	val8 = 0xf5;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
-#endif
-	i2c_write(0x26, 0x2, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-	val8 = 0;
-	i2c_write(0x27, 0x6, 1, &val8, 1);
-	i2c_write(0x27, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x27, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x27, 0x3, 1, &val8, 1);
-	asm("eieio");
-
-#if defined(PCI_64BIT)
-	printf("PCI1: 64-bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
-	printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
-#elif defined(PCI_ONE_PCI1)
-	printf("PCI1: 32-bit on PMC1\n");
-	printf("PCI2: 32-bit on PMC2, PMC3\n");
-#else
-	printf("PCI1: 32-bit on PMC1, PMC2\n");
-	printf("PCI2: 32-bit on PMC3\n");
-#endif
-	/* Reset to original I2C bus */
-	i2c_set_bus_num(orig_i2c_bus);
-}
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
-	/* initialize the PCA9555PW IO expander on the PIB board */
-	pib_init();
-
-	/* Enable all 8 PCI_CLK_OUTPUTS */
-	clk->occr = 0xff000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
-
-#else
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure PCI Inbound Translation Windows (3 1MB windows) */
-	pci_ctrl->pitar0 = 0x0;
-	pci_ctrl->pibar0 = 0x0;
-	pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			   PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar1  = 0x0;
-	pci_ctrl->pibar1  = 0x0;
-	pci_ctrl->piebar1 = 0x0;
-	pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar2  = 0x0;
-	pci_ctrl->pibar2  = 0x0;
-	pci_ctrl->piebar2 = 0x0;
-	pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	/* Unlock the configuration bit */
-	mpc83xx_pcislave_unlock(0);
-	printf("PCI:   Agent mode enabled\n");
-}
-#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig
deleted file mode 100644
index ce3fffd..0000000
--- a/board/freescale/mpc8349itx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8349ITX
-
-config SYS_BOARD
-	default "mpc8349itx"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8349ITX"
-
-endif
diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS
deleted file mode 100644
index d0388ad..0000000
--- a/board/freescale/mpc8349itx/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-MPC8349ITX BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc8349itx/
-F:	include/configs/MPC8349ITX.h
-F:	configs/MPC8349ITX_defconfig
-F:	configs/MPC8349ITX_LOWBOOT_defconfig
-F:	configs/MPC8349ITXGP_defconfig
diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile
deleted file mode 100644
index e9092ad..0000000
--- a/board/freescale/mpc8349itx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc8349itx.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README
deleted file mode 100644
index 48bbd50..0000000
--- a/board/freescale/mpc8349itx/README
+++ /dev/null
@@ -1,187 +0,0 @@
-Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
----------------------------------------------------
-
-1.	Board Description
-
-	The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
-	the Freescale MPC8349E processor in a Mini-ITX form factor.
-
-	The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
-
-	A) One 8MB on-board flash EEPROM chip, instead of two.
-	B) No SATA controller
-	C) No Compact Flash slot
-	D) No Mini-PCI slot
-	E) No Vitesse 7385 5-port Ethernet switch
-	F) No 4-port USB Type-A interface
-
-2.	Board Switches and Jumpers
-
-2.0	Descriptions for all of the board jumpers can be found in the User
-	Guide.  Of particular interest to U-Boot developers is jumper J22:
-
-	Pos.	Name		Default		Description
-	-----------------------------------------------------------------------
-	A	LGPL0		ON (0)          HRCW source, bit 0
-	B       LGPL1           ON (0)          HRCW source, bit 1
-	C       LGPL3           ON (0)		HRCW source, bit 2
-	D       LGPL5           OFF (1)         PCI_SYNC_OUT frequency
-	E       BOOT1           ON (0)          Flash EEPROM boot device
-	F       PCI_M66EN       ON (0)          PCI 66MHz enable
-	G       I2C-WP          ON (0)          I2C EEPROM write protection
-	H       F_WP            OFF (1)         Flash EEPROM write protection
-
-	Jumper J22.E is only for the ITX, and it decides the configuration
-	of the flash chips.  If J22.E is ON (i.e. jumpered), then flash chip
-	U4 is located at address FE000000 and flash chip U7 is at FE800000.
-	If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
-
-	For U-Boot development, J22.E can be used to switch back-and-forth
-	between two U-Boot images.
-
-3.	Memory Map
-
-3.1.	The memory map should look pretty much like this:
-
-	0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
-	0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
-	0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
-	0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
-	0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
-	0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
-	0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
-	0xF001_0000 - 0xF001_FFFF Local bus expansion slot
-	0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
-	0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
-	0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
-
-3.2	Flash EEPROM layout.
-
-	On the ITX, jumper J22.E is used to determine which flash chips are
-	at which address.  When J22.E is switched, addresses from FE000000
-	to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
-
-	On the ITX, at the normal boot address (aka HIGHBOOT):
-
-	FE00_0000	HRCW
-	FE70_0000	Alternative U-Boot image
-	FE80_0000	Alternative HRCW
-	FEF0_0000	U-Boot image
-	FEFF_FFFF	End of flash
-
-	On the ITX, at the low boot address (LOWBOOT)
-
-	FE00_0000	HRCW and U-Boot image
-	FE04_0000	U-Boot environment variables
-	FE80_0000	Alternative HRCW and U-Boot image
-	FEFF_FFFF	End of flash
-
-	On the ITX-GP, the only option is LOWBOOT and there is only one chip
-
-	FE00_0000	HRCW and U-Boot image
-	FE04_0000	U-Boot environment variables
-	F7FF_FFFF	End of flash
-
-4. Definitions
-
-4.1 Explanation of NEW definitions in:
-
-	include/configs/MPC8349ITX.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC8349		MPC8349 specific
-	CONFIG_MPC8349ITX		MPC8349E-mITX
-	CONFIG_MPC8349ITXGP		MPC8349E-mITX-GP
-
-5. Compilation
-
-	Assuming you're using BASH shell:
-
-		export CROSS_COMPILE=your-cross-compile-prefix
-		cd u-boot
-		make distclean
-
-		make MPC8349ITX_config
-	or:
-		make MPC8349ITXGP_config
-	or:
-		make MPC8349ITX_LOWBOOT_config
-
-		make
-
-6. Downloading and Flashing Images
-
-6.1 Download via tftp:
-
-	tftp $loadaddr <uboot>
-
-	where "<uboot>" is the path and filename, on the TFTP server, of
-	the U-Boot image.
-
-6.1 Reflash U-Boot Image using U-Boot
-
-	setenv uboot <uboot>
-	run tftpflash
-
-	where "<uboot>" is the path and filename, on the TFTP server, of
-	the U-Boot image.
-
-6.2 Using the HRCW to switch between two different U-Boot images on the ITX
-
-	Because the ITX has 16MB of flash, it is possible to keep two U-Boot
-	images in flash, and use the HRCW to specify which one is to be used
-	when the board boots.  This trick is especially effective with a
-	hardware debugger that can override the HRCW, such as the BDI-2000.
-
-	When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
-	at address FE000000.  When the BMS bit is 1, the ITX will boot the
-	image at address FEF00000.
-
-	Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
-	change the BMS bit whenever you want to boot the other image.
-
-	Step-by-step instructions:
-
-	1) Build an ITX image to be loaded at FEF00000
-
-		make distclean
-		make MPC8349ITX_config
-		make
-
-	2) Take the u-boot.bin image and flash it at FEF00000.
-
-		tftp $loadaddr u-boot.bin
-		protect off all
-		erase FEF00000 +$filesize
-		cp.b $loadaddr FEF00000 $filesize
-
-	3) Build an ITX image to be loaded at FE000000
-
-		make distclean
-		make MPC8349ITX_LOWBOOT_config
-		make
-
-	4) Take the u-boot.bin image and flash it at FE000000.
-
-		tftp $loadaddr u-boot.bin
-		protect off FE000000 +$filesize
-		erase FE000000 +$filesize
-		cp.b $loadaddr FE000000 $filesize
-
-	The HRCW in flash is currently set to boot the image at FE000000.
-
-	If you have a hardware debugger, configure it to set the HRCW to
-	B460A000 04040000 if you want to boot the image at FEF00000, or set
-	it to B060A000 04040000 if you want to boot the image at FE000000.
-
-	To change the HRCW in flash to boot the image at FEF00000, use these
-	U-Boot commands:
-
-		cp.b FE000000 1000 10000	; copy 1st flash sector to 1000
-		mw.b 1020 b4 8			; modify BMS bit
-		protect off FE000000 +10000
-		erase FE000000 +10000
-		cp.b 1000 FE000000 10000
-
-7. Notes
-	1) The console baudrate for MPC8349EITX is 115200bps.
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
deleted file mode 100644
index 22a1d99..0000000
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <vsc7385.h>
-#ifdef CONFIG_PCI
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#endif
-#include <spd_sdram.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-#ifndef CONFIG_SPD_EEPROM
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	/* The size of RAM, in bytes */
-	u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
-	u32 ddr_size_log2 = __ilog2(ddr_size);
-
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[0].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
-				CSBNDS_EA_SHIFT) & CSBNDS_EA);
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Only one CS for DDR */
-	im->ddr.cs_config[1] = 0;
-	im->ddr.cs_config[2] = 0;
-	im->ddr.cs_config[3] = 0;
-
-	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
-	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
-
-	debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
-	debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
-
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
-	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
-	im->ddr.sdram_mode =
-	    (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
-	im->ddr.sdram_interval =
-	    (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
-						       SDRAM_INTERVAL_BSTOPRE_SHIFT);
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
-	debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
-	debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
-	debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
-	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
-	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
-
-	return CONFIG_SYS_DDR_SIZE;
-}
-#endif
-
-#ifdef CONFIG_PCI
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
-	{
-	 PCI_ANY_ID,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID,
-	 0x0f,
-	 PCI_ANY_ID,
-	 pci_cfgfunc_config_device,
-	 {
-	  PCI_ENET0_IOADDR,
-	  PCI_ENET0_MEMADDR,
-	  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
-	 },
-	{}
-}
-#endif
-
-volatile static struct pci_controller hose[] = {
-	{
-#ifndef CONFIG_PCI_PNP
-	      config_table:pci_mpc83xxmitx_config_table,
-#endif
-	 },
-	{
-#ifndef CONFIG_PCI_PNP
-	      config_table:pci_mpc83xxmitx_config_table,
-#endif
-	 }
-};
-#endif				/* CONFIG_PCI */
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-#ifdef CONFIG_DDR_ECC
-	volatile ddr83xx_t *ddr = &im->ddr;
-#endif
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#ifdef CONFIG_SPD_EEPROM
-	msize = spd_sdram();
-#else
-	msize = fixed_sdram();
-#endif
-
-#ifdef CONFIG_DDR_ECC
-	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
-		/* Unlike every other board, on the 83xx spd_sdram() returns
-		   megabytes instead of just bytes.  That's why we need to
-		   multiple by 1MB when calling ddr_enable_ecc(). */
-		ddr_enable_ecc(msize * 1048576);
-#endif
-
-	/* return total bus RAM size(bytes) */
-	return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
-#ifdef CONFIG_MPC8349ITX
-	puts("Board: Freescale MPC8349E-mITX\n");
-#else
-	puts("Board: Freescale MPC8349E-mITX-GP\n");
-#endif
-
-	return 0;
-}
-
-/*
- * Implement a work-around for a hardware problem with compact
- * flash.
- *
- * Program the UPM if compact flash is enabled.
- */
-int misc_init_f(void)
-{
-#ifdef CONFIG_VSC7385_ENET
-	volatile u32 *vsc7385_cpuctrl;
-
-	/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
-	   default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
-	   means it is 0 when the IRQ is not active.  This makes the wire-AND
-	   logic always assert IRQ7 to CPU even if there is no request from the
-	   switch.  Since the compact flash and the switch share the same IRQ,
-	   the Linux kernel will think that the compact flash is requesting irq
-	   and get stuck when it tries to clear the IRQ.  Thus we need to set
-	   the L2_IRQ0 and L2_IRQ1 to active low.
-
-	   The following code sets the L1_IRQ and L2_IRQ polarity to active low.
-	   Without this code, compact flash will not work in Linux because
-	   unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
-	   don't enable compact flash for U-Boot.
-	 */
-
-	vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
-	*vsc7385_cpuctrl |= 0x0c;
-#endif
-
-#ifdef CONFIG_COMPACT_FLASH
-	/* UPM Table Configuration Code */
-	static uint UPMATable[] = {
-		0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
-		0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
-		0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
-	};
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
-	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
-
-	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
-	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
-	 */
-	immap->im_lbc.mamr = 0x08404440;
-
-	upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
-
-	puts("UPMA:  Configured for compact flash\n");
-#endif
-
-	return 0;
-}
-
-/*
- * Miscellaneous late-boot configurations
- *
- * Make sure the EEPROM has the HRCW correctly programmed.
- * Make sure the RTC is correctly programmed.
- *
- * The MPC8349E-mITX can be configured to load the HRCW from
- * EEPROM instead of flash.  This is controlled via jumpers
- * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
- * jumpered), but if they're set to 001 or 010, then the HRCW is
- * read from the "I2C EEPROM".
- *
- * This function makes sure that the I2C EEPROM is programmed
- * correctly.
- *
- * If a VSC7385 microcode image is present, then upload it.
- */
-int misc_init_r(void)
-{
-	int rc = 0;
-
-#if defined(CONFIG_SYS_I2C)
-	unsigned int orig_bus = i2c_get_bus_num();
-	u8 i2c_data;
-
-#ifdef CONFIG_SYS_I2C_RTC_ADDR
-	u8 ds1339_data[17];
-#endif
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
-	static u8 eeprom_data[] =	/* HRCW data */
-	{
-		0xAA, 0x55, 0xAA,       /* Preamble */
-		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
-		0x02, 0x40,	        /* RCWL ADDR=0x0_0900 */
-		(CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
-		(CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
-		(CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
-		CONFIG_SYS_HRCW_LOW & 0xFF,
-		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
-		0x02, 0x41,	        /* RCWH ADDR=0x0_0904 */
-		(CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
-		(CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
-		(CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
-		CONFIG_SYS_HRCW_HIGH & 0xFF
-	};
-
-	u8 data[sizeof(eeprom_data)];
-#endif
-
-	printf("Board revision: ");
-	i2c_set_bus_num(1);
-	if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
-		printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
-	else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
-		printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
-	else {
-		printf("Unknown\n");
-		rc = 1;
-	}
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
-	i2c_set_bus_num(0);
-
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
-		if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
-			if (i2c_write
-			    (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
-			     sizeof(eeprom_data)) != 0) {
-				puts("Failure writing the HRCW to EEPROM via I2C.\n");
-				rc = 1;
-			}
-		}
-	} else {
-		puts("Failure reading the HRCW from EEPROM via I2C.\n");
-		rc = 1;
-	}
-#endif
-
-#ifdef CONFIG_SYS_I2C_RTC_ADDR
-	i2c_set_bus_num(1);
-
-	if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
-	    == 0) {
-
-		/* Work-around for MPC8349E-mITX bug #13601.
-		   If the RTC does not contain valid register values, the DS1339
-		   Linux driver will not work.
-		 */
-
-		/* Make sure status register bits 6-2 are zero */
-		ds1339_data[0x0f] &= ~0x7c;
-
-		/* Check for a valid day register value */
-		ds1339_data[0x03] &= ~0xf8;
-		if (ds1339_data[0x03] == 0) {
-			ds1339_data[0x03] = 1;
-		}
-
-		/* Check for a valid date register value */
-		ds1339_data[0x04] &= ~0xc0;
-		if ((ds1339_data[0x04] == 0) ||
-		    ((ds1339_data[0x04] & 0x0f) > 9) ||
-		    (ds1339_data[0x04] >= 0x32)) {
-			ds1339_data[0x04] = 1;
-		}
-
-		/* Check for a valid month register value */
-		ds1339_data[0x05] &= ~0x60;
-
-		if ((ds1339_data[0x05] == 0) ||
-		    ((ds1339_data[0x05] & 0x0f) > 9) ||
-		    ((ds1339_data[0x05] >= 0x13)
-		     && (ds1339_data[0x05] <= 0x19))) {
-			ds1339_data[0x05] = 1;
-		}
-
-		/* Enable Oscillator and rate select */
-		ds1339_data[0x0e] = 0x1c;
-
-		/* Work-around for MPC8349E-mITX bug #13330.
-		   Ensure that the RTC control register contains the value 0x1c.
-		   This affects SATA performance.
-		 */
-
-		if (i2c_write
-		    (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
-		     sizeof(ds1339_data))) {
-			puts("Failure writing to the RTC via I2C.\n");
-			rc = 1;
-		}
-	} else {
-		puts("Failure reading from the RTC via I2C.\n");
-		rc = 1;
-	}
-#endif
-
-	i2c_set_bus_num(orig_bus);
-#endif
-
-#ifdef CONFIG_VSC7385_IMAGE
-	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
-		CONFIG_VSC7385_IMAGE_SIZE)) {
-		puts("Failure uploading VSC7385 microcode.\n");
-		rc = 1;
-	}
-#endif
-
-	return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
deleted file mode 100644
index afc9df0..0000000
--- a/board/freescale/mpc8349itx/pci.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
-		size: CONFIG_SYS_PCI2_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_IO_BASE,
-		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
-		size: CONFIG_SYS_PCI2_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
-		size: CONFIG_SYS_PCI2_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-#endif
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-	u8 reg8;
-
-#if defined(CONFIG_SYS_I2C)
-	i2c_set_bus_num(1);
-	/* Read the PCI_M66EN jumper setting */
-	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
-	    (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
-		if (reg8 & I2C_8574_PCI66)
-			clk->occr = 0xff000000;	/* 66 MHz PCI */
-		else
-			clk->occr = 0xff600001;	/* 33 MHz PCI */
-	} else {
-		clk->occr = 0xff600001;	/* 33 MHz PCI */
-	}
-#else
-	clk->occr = 0xff000000;	/* 66 MHz PCI */
-#endif
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig
deleted file mode 100644
index 20d29db..0000000
--- a/board/freescale/mpc837xemds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC837XEMDS
-
-config SYS_BOARD
-	default "mpc837xemds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC837XEMDS"
-
-endif
diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS
deleted file mode 100644
index 6ff1346..0000000
--- a/board/freescale/mpc837xemds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC837XEMDS BOARD
-M:	Dave Liu <daveliu@freescale.com>
-S:	Maintained
-F:	board/freescale/mpc837xemds/
-F:	include/configs/MPC837XEMDS.h
-F:	configs/MPC837XEMDS_defconfig
-F:	configs/MPC837XEMDS_HOST_defconfig
diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile
deleted file mode 100644
index 70b2147..0000000
--- a/board/freescale/mpc837xemds/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc837xemds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README
deleted file mode 100644
index faf21c9..0000000
--- a/board/freescale/mpc837xemds/README
+++ /dev/null
@@ -1,104 +0,0 @@
-Freescale MPC837xEMDS Board
------------------------------------------
-1.	Board Switches and Jumpers
-1.0	There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
-	For some reason, the HW designers describe the switch settings
-	in terms of 0 and 1, and then map that to physical switches where
-	the label "On" refers to logic 0 and "Off" is logic 1.
-
-	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
-	bits may contribute to signals that are numbered based at 0,
-	and some of those signals may be high-bit-number-0 too.  Heed
-	well the names and labels and do not get confused.
-
-		"Off" == 1
-		"On"  == 0
-
-	SW4[8] is the bit labeled 8 on Switch 4.
-	SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
-	SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
-		and bits labeled 8 is set as "Off".
-
-1.1	For the MPC837xEMDS Processor Board
-
-	First, make sure the board default setting is consistent with the
-	document shipped with your board. Then apply the following setting:
-	SW3[1-8]= 0011_0000  (BOOTSEQ, ROMLOC setting)
-	SW4[1-8]= 0000_0110  (core PLL setting)
-	SW5[1-8]= 1001_1000  (system PLL, boot up from low end of flash)
-	SW6[1-8]= 0000_1000  (HRCW is read from NOR FLASH)
-	SW7[1-8]= 0110_1101  (TSEC1/2 interface setting - RGMII)
-	J3 2-3, TSEC1 LVDD1 with 2.5V
-	J6 2-3, TSEC2 LVDD2 with 2.5V
-	J9 2-3, CLKIN from osc on board
-	J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
-	J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
-	    mounted, HRCW load from BCSR.
-
-	on board Oscillator: 66M
-
-2.	Memory Map
-
-2.1.	The memory map should look pretty much like this:
-
-	0x0000_0000	0x7fff_ffff	DDR			2G
-	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
-	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
-	0xc000_0000	0xdfff_ffff	Empty			512M
-	0xe000_0000	0xe00f_ffff	Int Mem Reg Space	1M
-	0xe010_0000	0xe02f_ffff	Empty			2M
-	0xe030_0000	0xe03f_ffff	PCI IO			1M
-	0xe040_0000	0xe05f_ffff	Empty			2M
-	0xe060_0000	0xe060_7fff	NAND Flash		32K
-	0xf400_0000	0xf7ff_ffff	Empty			64M
-	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
-	0xfe00_0000	0xffff_ffff	NOR Flash on CS0	32M
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
-	include/configs/MPC837XEMDS.h
-
-    CONFIG_MPC83xx	    MPC83xx family for both MPC837x and MPC8360
-    CONFIG_MPC837x	    MPC837x specific
-    CONFIG_MPC837XEMDS	    MPC837XEMDS board specific
-
-4. Compilation
-
-	Assuming you're using BASH shell:
-
-		export CROSS_COMPILE=your-cross-compile-prefix
-		cd u-boot
-		make distclean
-		make MPC837XEMDS_config
-		make
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
-	loadb
-	[Drop to kermit:
-	    ^\c
-	    send <u-boot-bin-image>
-	    c
-	]
-
-
-    Or via tftp:
-
-	tftp 40000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
-	tftp 40000 u-boot.bin
-	protect off fe000000 fe1fffff
-	erase fe000000 fe1fffff
-
-	cp.b 40000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-
-6. Notes
-	1) The console baudrate for MPC837XEMDS is 115200bps.
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
deleted file mode 100644
index 572913c..0000000
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include <spd_sdram.h>
-#include <tsec.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_esdhc.h>
-#include <fsl_mdio.h>
-#include <phy.h>
-#include "pci.h"
-#include "../common/pq-mds-pib.h"
-
-int board_early_init_f(void)
-{
-	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
-	/* Enable flash write */
-	bcsr[0x9] &= ~0x04;
-	/* Clear all of the interrupt of BCSR */
-	bcsr[0xe] = 0xff;
-
-#ifdef CONFIG_FSL_SERDES
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	u32 spridr = in_be32(&immr->sysconf.spridr);
-
-	/* we check only part num, and don't look for CPU revisions */
-	switch (PARTID_NO_E(spridr)) {
-	case SPR_8377:
-		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
-				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		break;
-	case SPR_8378:
-		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
-				FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
-		break;
-	case SPR_8379:
-		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
-				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
-				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		break;
-	default:
-		printf("serdes not configured: unknown CPU part number: "
-				"%04x\n", spridr >> 16);
-		break;
-	}
-#endif /* CONFIG_FSL_SERDES */
-	return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(bd_t *bd)
-{
-	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
-	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
-	if (!hwconfig("esdhc"))
-		return 0;
-
-	/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
-	bcsr[0xc] |= 0x4c;
-
-	/* Set proper bits in SICR to allow SD signals through */
-	clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
-	clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
-			SICRH_GPIO2_E_SD | SICRH_SPI_SD);
-
-	return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
-int board_eth_init(bd_t *bd)
-{
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
-	u32 rcwh = in_be32(&im->reset.rcwh);
-	u32 tsec_mode;
-	int num = 0;
-
-	/* New line after Net: */
-	printf("\n");
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-
-	printf(CONFIG_TSEC1_NAME ": ");
-
-	tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
-	if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
-		printf("RGMII\n");
-		/* this is default, no need to fixup */
-	} else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
-		printf("SGMII\n");
-		tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
-		tsec_info[num].flags = TSEC_GIGABIT;
-	} else {
-		printf("unsupported PHY type\n");
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-
-	printf(CONFIG_TSEC2_NAME ": ");
-
-	tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
-	if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
-		printf("RGMII\n");
-		/* this is default, no need to fixup */
-	} else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
-		printf("SGMII\n");
-		tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
-		tsec_info[num].flags = TSEC_GIGABIT;
-	} else {
-		printf("unsupported PHY type\n");
-	}
-	num++;
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bd, &mdio_info);
-
-	return tsec_eth_init(bd, tsec_info, num);
-}
-
-static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
-			    int phy_addr)
-{
-	const u32 *ph;
-	int off;
-	int err;
-
-	off = fdt_path_offset(blob, alias);
-	if (off < 0) {
-		printf("WARNING: could not find %s alias: %s.\n", alias,
-			fdt_strerror(off));
-		return;
-	}
-
-	err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
-
-	if (err) {
-		printf("WARNING: could not set phy-connection-type for %s: "
-			"%s.\n", alias, fdt_strerror(err));
-		return;
-	}
-
-	ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
-	if (!ph) {
-		printf("WARNING: could not get phy-handle for %s.\n",
-			alias);
-		return;
-	}
-
-	off = fdt_node_offset_by_phandle(blob, *ph);
-	if (off < 0) {
-		printf("WARNING: could not get phy node for %s: %s\n", alias,
-			fdt_strerror(off));
-		return;
-	}
-
-	phy_addr = cpu_to_fdt32(phy_addr);
-	err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
-	if (err < 0) {
-		printf("WARNING: could not set phy node's reg for %s: "
-			"%s.\n", alias, fdt_strerror(err));
-		return;
-	}
-}
-
-static void ft_tsec_fixup(void *blob, bd_t *bd)
-{
-	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
-	u32 rcwh = in_be32(&im->reset.rcwh);
-	u32 tsec_mode;
-
-#ifdef CONFIG_TSEC1
-	tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
-	if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
-		__ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
-#endif
-
-#ifdef CONFIG_TSEC2
-	tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
-	if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
-		__ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
-#endif
-}
-#else
-static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
-#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
-	pib_init();
-#endif
-	return 0;
-}
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-#if defined(CONFIG_SPD_EEPROM)
-	msize = spd_sdram();
-#else
-	msize = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/* Initialize DDR ECC byte */
-	ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
-	/* return total bus DDR size(bytes) */
-	return (msize * 1024 * 1024);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-
-#if (CONFIG_SYS_DDR_SIZE != 512)
-#warning Currenly any ddr size other than 512 is not supported
-#endif
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-	udelay(50000);
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-	udelay(1000);
-
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	udelay(1000);
-
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__("sync");
-	udelay(1000);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	udelay(2000);
-	return CONFIG_SYS_DDR_SIZE;
-}
-#endif /*!CONFIG_SYS_SPD_EEPROM */
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC837xEMDS\n");
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-int board_pci_host_broken(void)
-{
-	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
-	const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
-
-	/* It's always OK in case of external arbiter. */
-	if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
-		return 0;
-
-	if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
-		return 1;
-
-	return 0;
-}
-
-static void ft_pci_fixup(void *blob, bd_t *bd)
-{
-	const char *status = "broken (no arbiter)";
-	int off;
-	int err;
-
-	off = fdt_path_offset(blob, "pci0");
-	if (off < 0) {
-		printf("WARNING: could not find pci0 alias: %s.\n",
-			fdt_strerror(off));
-		return;
-	}
-
-	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
-	if (err) {
-		printf("WARNING: could not set status for pci0: %s.\n",
-			fdt_strerror(err));
-		return;
-	}
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	ft_tsec_fixup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
-	fdt_fixup_esdhc(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-	if (board_pci_host_broken())
-		ft_pci_fixup(blob, bd);
-	ft_pcie_fixup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
deleted file mode 100644
index 39c40e5..0000000
--- a/board/freescale/mpc837xemds/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fdt_support.h>
-#include <asm/fsl_i2c.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
-		size: CONFIG_SYS_PCI_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
-		size: CONFIG_SYS_PCI_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_IO_BASE,
-		phys_start: CONFIG_SYS_PCI_IO_PHYS,
-		size: CONFIG_SYS_PCI_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static int is_pex_x2(void)
-{
-	const char *pex_x2 = getenv("pex_x2");
-
-	if (pex_x2 && !strcmp(pex_x2, "yes"))
-		return 1;
-	return 0;
-}
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-	u32 spridr = in_be32(&immr->sysconf.spridr);
-	int pex2 = is_pex_x2();
-
-	if (board_pci_host_broken())
-		goto skip_pci;
-
-	/* Enable all 5 PCI_CLK_OUTPUTS */
-	clk->occr |= 0xf8000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	udelay(2000);
-
-	mpc83xx_pci_init(1, reg);
-skip_pci:
-	/* There is no PEX in MPC8379 parts. */
-	if (PARTID_NO_E(spridr) == SPR_8379)
-		return;
-
-	if (pex2)
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-	else
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
-	/* Configure the clock for PCIE controller */
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
-				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	if (!pex2)
-		out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
-}
-
-void ft_pcie_fixup(void *blob, bd_t *bd)
-{
-	const char *status = "disabled (PCIE1 is x2)";
-
-	if (!is_pex_x2())
-		return;
-
-	do_fixup_by_path(blob, "pci2", "status", status,
-			 strlen(status) + 1, 1);
-}
diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h
deleted file mode 100644
index fd7a916..0000000
--- a/board/freescale/mpc837xemds/pci.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BOARD_MPC837XEMDS_PCI_H
-#define __BOARD_MPC837XEMDS_PCI_H
-
-extern void ft_pcie_fixup(void *blob, bd_t *bd);
-
-#endif /* __BOARD_MPC837XEMDS_PCI_H */
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
deleted file mode 100644
index 64717ec..0000000
--- a/configs/MPC8308RDB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8308RDB=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
deleted file mode 100644
index ca6c304..0000000
--- a/configs/MPC8313ERDB_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
deleted file mode 100644
index 974bdf9..0000000
--- a/configs/MPC8313ERDB_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
deleted file mode 100644
index ba81885..0000000
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
deleted file mode 100644
index afe8740..0000000
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
deleted file mode 100644
index ebebbed..0000000
--- a/configs/MPC8315ERDB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8315ERDB=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
deleted file mode 100644
index 7c03842..0000000
--- a/configs/MPC8323ERDB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8323ERDB=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
deleted file mode 100644
index e1ba08d..0000000
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
deleted file mode 100644
index 55df0f6..0000000
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
deleted file mode 100644
index 1ceee68..0000000
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
deleted file mode 100644
index ef67be5..0000000
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
deleted file mode 100644
index 0398472..0000000
--- a/configs/MPC832XEMDS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
deleted file mode 100644
index f6af218..0000000
--- a/configs/MPC8349EMDS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8349EMDS=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
deleted file mode 100644
index f853309..0000000
--- a/configs/MPC8349ITXGP_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8349ITX=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
deleted file mode 100644
index 5321801..0000000
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8349ITX=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
deleted file mode 100644
index 83f25ae..0000000
--- a/configs/MPC8349ITX_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8349ITX=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
deleted file mode 100644
index d3be43a..0000000
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC837XEMDS=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
deleted file mode 100644
index d3b7c1d..0000000
--- a/configs/MPC837XEMDS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC837XEMDS=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 59d2142..b8c9f9c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,14 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+MPC8308RDB       powerpc     mpc83xx        -           -           Ilya Yanok <yanok@emcraft.com>
+MPC8313ERDB      powerpc     mpc83xx        -           -
+MPC8315ERDB      powerpc     mpc83xx        -           -           Dave Liu <daveliu@freescale.com>
+MPC8323ERDB      powerpc     mpc83xx        -           -           Michael Barkowski <michael.barkowski@freescale.com>
+MPC832XEMDS      powerpc     mpc83xx        -           -           Dave Liu <daveliu@freescale.com>
+MPC8349EMDS      powerpc     mpc83xx        -           -           Kim Phillips <kim.phillips@freescale.com>
+MPC8349ITX       powerpc     mpc83xx        -           -
+MPC837XEMDS      powerpc     mpc83xx        -           -           Dave Liu <daveliu@freescale.com>
 korat            powerpc     ppc4xx         -           -           Larry Johnson <lrj@acm.org>
 galaxy5200       powerpc     mpc5xxx        -           -           Eric Millbrandt <emillbrandt@dekaresearch.com>
 W7OLMC           powerpc     ppc4xx         -           -           Erik Theisen <etheisen@mindspring.com>
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
deleted file mode 100644
index bf974fd..0000000
--- a/include/configs/MPC8308RDB.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC830x		1 /* MPC830x family */
-#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
-#define CONFIG_MPC8308RDB	1 /* MPC8308RDB board specific */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-
-#define CONFIG_MISC_INIT_R
-
-/* new uImage format support */
-#define CONFIG_FIT			1
-#define CONFIG_FIT_VERBOSE		1
-
-#define CONFIG_MMC     1
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ESDHC_USE_PIO
-
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * On-board devices
- *
- * TSEC1 is SoC TSEC
- * TSEC2 is VSC switch
- */
-#define CONFIG_TSEC1
-#define CONFIG_VSC7385_ENET
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
-	HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
-	SICRH_ESDHC_A_SD |\
-	SICRH_ESDHC_B_SD |\
-	SICRH_ESDHC_C_SD |\
-	SICRH_GPIO_A_TSEC2 |\
-	SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
-	SICRH_IEEE1588_A_GPIO |\
-	SICRH_USB |\
-	SICRH_GTM_GPIO |\
-	SICRH_IEEE1588_B_GPIO |\
-	SICRH_ETSEC2_CRS |\
-	SICRH_GPIOSEL_1 |\
-	SICRH_TMROBI_V3P3 |\
-	SICRH_TSOBI1_V2P5 |\
-	SICRH_TSOBI2_V2P5)	/* 0x01b7d103 */
-#define CONFIG_SYS_SICRL (\
-	SICRL_SPI_PF0 |\
-	SICRL_UART_PF0 |\
-	SICRL_IRQ_PF0 |\
-	SICRL_I2C2_PF0 |\
-	SICRL_ETSEC1_GTX_CLK125)	/* 0x00000040 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
-/*
- * SERDES
- */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1	0xe3000
-
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
-				| DDRCDR_PZ_LOZ \
-				| DDRCDR_NZ_LOZ \
-				| DDRCDR_ODT \
-				| DDRCDR_Q_DRN)
-				/* 0x7b880001 */
-/*
- * Manually set up DDR parameters
- * consist of two chips HY5PS12621BFP-C4 from HYNIX
- */
-
-#define CONFIG_SYS_DDR_SIZE		128 /* MB */
-
-#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-				| CSCONFIG_ODT_RD_NEVER \
-				| CSCONFIG_ODT_WR_ONLY_CURRENT \
-				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
-				/* 0x80010102 */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
-				| (0 << TIMING_CFG0_WRT_SHIFT) \
-				| (0 << TIMING_CFG0_RRT_SHIFT) \
-				| (0 << TIMING_CFG0_WWT_SHIFT) \
-				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
-				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
-				/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
-				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
-				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
-				| (6 << TIMING_CFG1_REFREC_SHIFT) \
-				| (2 << TIMING_CFG1_WRREC_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
-				| (2 << TIMING_CFG1_WRTORD_SHIFT))
-				/* 0x27256222 */
-#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
-				| (4 << TIMING_CFG2_CPO_SHIFT) \
-				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
-				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
-				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
-				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
-				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
-				/* 0x121048c5 */
-#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
-				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
-				/* 0x03600100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
-				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_DBW_32)
-				/* 0x43080000 */
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
-				| (0x0232 << SDRAM_MODE_SD_SHIFT))
-				/* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2		0x00000000
-
-/*
- * Memory test
- */
-#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x07f00000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR		0x00040000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
-#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
-
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16	/* 16 bit port */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_UPM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
-/* 127 64KB sectors and 8 8KB top sectors per device */
-#define CONFIG_SYS_MAX_FLASH_SECT	135
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_SYS_NAND_BASE	0xE0600000		/* 0xE0600000 */
-#define CONFIG_SYS_NAND_WINDOW_SIZE	(32 * 1024)	/* 0x00008000 */
-#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE \
-				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
-				| BR_PS_8		/* 8 bit Port */ \
-				| BR_MS_FCM		/* MSEL = FCM */ \
-				| BR_V)			/* valid */
-#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
-				| OR_FCM_CSCT \
-				| OR_FCM_CST \
-				| OR_FCM_CHT \
-				| OR_FCM_SCY_1 \
-				| OR_FCM_TRLX \
-				| OR_FCM_EHTR)
-				/* 0xFFFF8396 */
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
-					/* VSC7385 Base address on CS2 */
-#define CONFIG_SYS_VSC7385_BASE		0xF0000000
-#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024) /* 0x00020000 */
-#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
-					| BR_PS_8	/* 8-bit port */ \
-					| BR_MS_GPCM	/* MSEL = GPCM */ \
-					| BR_V)		/* valid */
-					/* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
-					| OR_GPCM_CSNT \
-					| OR_GPCM_XACS \
-					| OR_GPCM_SCY_15 \
-					| OR_GPCM_SETA \
-					| OR_GPCM_TRLX_SET \
-					| OR_GPCM_EHTR_SET)
-					/* 0xFFFE09FF */
-/* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
-/* Access window size 128K */
-#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE		0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE	8192
-#endif
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
-
-/*
- * SPI on header J8
- *
- * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
- * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-#define CONFIG_CMD_SPI
-#define CONFIG_USE_SPIFLASH
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_CMD_SF
-#endif
-
-/*
- * Board info - revision and where boot from
- */
-#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCIE1_BASE		0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
-
-/* enable PCIE clock */
-#define CONFIG_SYS_SCCR_PCIEXP1CM	1
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE
-
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
-#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET	0x25000
-#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_MII		1 /* MII PHY management */
-#define CONFIG_TSEC1_NAME	"eTSEC0"
-#define CONFIG_TSEC2_NAME	"eTSEC1"
-#define TSEC1_PHY_ADDR		2
-#define TSEC2_PHY_ADDR		1
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#define TSEC2_FLAGS		TSEC_GIGABIT
-
-/* Options are: eTSEC[0-1] */
-#define CONFIG_ETHPRIME		"eTSEC0"
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
-				 CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-
-#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE | \
-				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2		HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
-					BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
-					BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
-			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
-					BATU_VP)
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
-					BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
-					BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
-					BATL_CACHEINHIBIT | \
-					BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
-					BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consoledev=ttyS0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs}"				\
-		" console=${consoledev},${baudrate}\0"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addmisc=setenv bootargs ${bootargs}\0"				\
-	"kernel_addr=FE080000\0"					\
-	"fdt_addr=FE280000\0"						\
-	"ramdisk_addr=FE290000\0"					\
-	"u-boot=mpc8308rdb/u-boot.bin\0"				\
-	"kernel_addr_r=1000000\0"					\
-	"fdt_addr_r=C00000\0"						\
-	"hostname=mpc8308rdb\0"						\
-	"bootfile=mpc8308rdb/uImage\0"					\
-	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"				\
-	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
-	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"bootcmd=run flash_self\0"					\
-	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
-		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
-		" +${filesize};cp.b ${fileaddr} "			\
-		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
-	"upd=run load update\0"						\
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
deleted file mode 100644
index dd81229..0000000
--- a/include/configs/MPC8313ERDB.h
+++ /dev/null
@@ -1,719 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*
- * mpc8313epb board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1
-#define CONFIG_MPC831x		1
-#define CONFIG_MPC8313		1
-#define CONFIG_MPC8313ERDB	1
-
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
-#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SPL_MAX_SIZE	(4 * 1024)
-#define CONFIG_SPL_PAD_TO	0x4000
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#endif
-
-#endif /* CONFIG_NAND */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFE000000
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_ELBC 1
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- *
- * TSEC1 is VSC switch
- * TSEC2 is SoC TSEC
- */
-#define CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
-
-#ifdef CONFIG_SYS_66MHZ
-#define CONFIG_83XX_CLKIN	66666667	/* in Hz */
-#elif defined(CONFIG_SYS_33MHZ)
-#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
-#else
-#error Unknown oscillator frequency.
-#endif
-
-#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
-
-#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f */
-#define CONFIG_BOARD_EARLY_INIT_R		/* call board_early_init_r */
-
-#define CONFIG_SYS_IMMR		0xE0000000
-
-#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
-#endif
-
-#define CONFIG_SYS_MEMTEST_START	0x00001000
-#define CONFIG_SYS_MEMTEST_END		0x07f00000
-
-/* Early revs of this board will lock up hard when attempting
- * to access the PMC registers, unless a JTAG debugger is
- * connected, or some resistor modifications are made.
- */
-#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-
-#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
-
-/*
- * Device configurations
- */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC1
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE		0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE	8192
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-
-/*
- * Manually set up DDR parameters, as this board does not
- * seem to have the SPD connected to I2C.
- */
-#define CONFIG_SYS_DDR_SIZE	128		/* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-				| CSCONFIG_ODT_RD_NEVER \
-				| CSCONFIG_ODT_WR_ONLY_CURRENT \
-				| CSCONFIG_ROW_BIT_13 \
-				| CSCONFIG_COL_BIT_10)
-				/* 0x80010102 */
-
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
-				| (0 << TIMING_CFG0_WRT_SHIFT) \
-				| (0 << TIMING_CFG0_RRT_SHIFT) \
-				| (0 << TIMING_CFG0_WWT_SHIFT) \
-				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
-				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
-				/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
-				| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
-				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
-				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
-				| (10 << TIMING_CFG1_REFREC_SHIFT) \
-				| (3 << TIMING_CFG1_WRREC_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
-				| (2 << TIMING_CFG1_WRTORD_SHIFT))
-				/* 0x3835a322 */
-#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
-				| (5 << TIMING_CFG2_CPO_SHIFT) \
-				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
-				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
-				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
-				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
-				| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
-				/* 0x129048c6 */ /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_INTERVAL	((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
-				| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
-				/* 0x05100500 */
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
-				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_DBW_32 \
-				| SDRAM_CFG_2T_EN)
-				/* 0x43088000 */
-#else
-#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
-				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_DBW_32)
-				/* 0x43080000 */
-#endif
-#define CONFIG_SYS_SDRAM_CFG2		0x00401000
-/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
-				| (0x0632 << SDRAM_MODE_SD_SHIFT))
-				/* 0x44480632 */
-#define CONFIG_SYS_DDR_MODE_2	0x8000C000
-
-#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-				/*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
-				| DDRCDR_PZ_NOMZ \
-				| DDRCDR_NZ_NOMZ \
-				| DDRCDR_M_ODR)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE		8	/* flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
-
-#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
-					| BR_PS_16	/* 16 bit port */ \
-					| BR_MS_GPCM	/* MSEL = GPCM */ \
-					| BR_V)		/* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_9 \
-				| OR_GPCM_EHTR \
-				| OR_GPCM_EAD)
-				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
-					/* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-					/* 16 MB window size */
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_16MB)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	135	/* sectors per device */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
-	!defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
-				| (0xFF << LBCR_BMT_SHIFT) \
-				| 0xF)	/* 0x0004ff0f */
-
-				/* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */
-
-/* drivers/mtd/nand/nand.c */
-#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_BASE		0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE		0xE2800000
-#endif
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITION
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT			"nand0=e2800000.flash"
-#define MTDPARTS_DEFAULT		\
-	"mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
-
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-
-
-#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
-				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
-				| BR_PS_8		/* 8 bit port */ \
-				| BR_MS_FCM		/* MSEL = FCM */ \
-				| BR_V)			/* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM	\
-				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
-				| OR_FCM_CSCT \
-				| OR_FCM_CST \
-				| OR_FCM_CHT \
-				| OR_FCM_SCY_1 \
-				| OR_FCM_TRLX \
-				| OR_FCM_EHTR)
-				/* 0xFFFF8396 */
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#endif
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-/* local bus write LED / read status buffer (BCSR) mapping */
-#define CONFIG_SYS_BCSR_ADDR		0xFA000000
-#define CONFIG_SYS_BCSR_SIZE		(32 * 1024)	/* 0x00008000 */
-					/* map at 0xFA000000 on LCS3 */
-#define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_BCSR_ADDR \
-					| BR_PS_8	/* 8 bit port */ \
-					| BR_MS_GPCM	/* MSEL = GPCM */ \
-					| BR_V)		/* valid */
-					/* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
-					| OR_GPCM_CSNT \
-					| OR_GPCM_ACS_DIV2 \
-					| OR_GPCM_XACS \
-					| OR_GPCM_SCY_15 \
-					| OR_GPCM_TRLX_SET \
-					| OR_GPCM_EHTR_SET \
-					| OR_GPCM_EAD)
-					/* 0xFFFF8FF7 */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_BCSR_ADDR
-#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-					/* VSC7385 Base address on LCS2 */
-#define CONFIG_SYS_VSC7385_BASE		0xF0000000
-#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024)	/* 0x00020000 */
-
-#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
-					| BR_PS_8	/* 8 bit port */ \
-					| BR_MS_GPCM	/* MSEL = GPCM */ \
-					| BR_V)		/* valid */
-#define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
-					| OR_GPCM_CSNT \
-					| OR_GPCM_XACS \
-					| OR_GPCM_SCY_15 \
-					| OR_GPCM_SETA \
-					| OR_GPCM_TRLX_SET \
-					| OR_GPCM_EHTR_SET \
-					| OR_GPCM_EAD)
-					/* 0xFFFE09FF */
-
-					/* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
-
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-#define CONFIG_MPC83XX_GPIO 1
-#define CONFIG_CMD_GPIO 1
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
-
-#define CONFIG_GMII			/* MII PHY management */
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define TSEC1_PHY_ADDR		0x1c
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#define TSEC1_PHYIDX		0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME	"TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET	0x25000
-#define TSEC2_PHY_ADDR		4
-#define TSEC2_FLAGS		TSEC_GIGABIT
-#define TSEC2_PHYIDX		0
-#endif
-
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME			"TSEC1"
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
-
-/*
- * Environment
- */
-#if defined(CONFIG_NAND)
-	#define CONFIG_ENV_IS_IN_NAND	1
-	#define CONFIG_ENV_OFFSET		(512 * 1024)
-	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
-	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
-	#define CONFIG_ENV_OFFSET_REDUND	\
-					(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#elif !defined(CONFIG_SYS_RAMBOOT)
-	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		\
-			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
-	#define CONFIG_ENV_SIZE		0x2000
-
-/* Address and size of Redundant Environment Sector */
-#else
-	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-	#define CONFIG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PCI
-
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
-    #undef CONFIG_CMD_SAVEENV
-    #undef CONFIG_CMD_LOADS
-#endif
-
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
-
-						/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	\
-			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-				/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-				/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
-
-#ifdef CONFIG_SYS_66MHZ
-
-/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
-/* 0x62040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-	0x20000000 /* reserved, must be set */ |\
-	HRCWL_DDRCM |\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
-
-#elif defined(CONFIG_SYS_33MHZ)
-
-/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
-/* 0x65040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-	0x20000000 /* reserved, must be set */ |\
-	HRCWL_DDRCM |\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_CSB_TO_CLKIN_5X1 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
-
-#endif
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN)
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-		       HRCWH_FROM_0XFFF00100 |\
-		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
-		       HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-		       HRCWH_FROM_0X00000100 |\
-		       HRCWH_ROM_LOC_LOCAL_16BIT |\
-		       HRCWH_RL_EXT_LEGACY)
-#endif
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
-			/* Enable Internal USB Phy and GPIO on LCD Connector */
-#define CONFIG_SYS_SICRL	(SICRL_USBDR_10 | SICRL_LBC)
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE | \
-				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* PCI2 not supported on 8313 */
-#define CONFIG_SYS_IBAT3L	(0)
-#define CONFIG_SYS_IBAT3U	(0)
-#define CONFIG_SYS_IBAT4L	(0)
-#define CONFIG_SYS_IBAT4U	(0)
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV		"eth1"
-
-#define CONFIG_HOSTNAME		mpc8313erdb
-#define CONFIG_ROOTPATH		"/nfs/root/path"
-#define CONFIG_BOOTFILE		"uImage"
-				/* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH	"u-boot.bin"
-#define CONFIG_FDTFILE		"mpc8313erdb.dtb"
-
-				/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		800000
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"netdev=" CONFIG_NETDEV "\0"					\
-	"ethprime=TSEC1\0"						\
-	"uboot=" CONFIG_UBOOTPATH "\0"					\
-	"tftpflash=tftpboot $loadaddr $uboot; "				\
-		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" +$filesize; "	\
-		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize; "	\
-		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize\0"	\
-	"fdtaddr=780000\0"						\
-	"fdtfile=" CONFIG_FDTFILE "\0"					\
-	"console=ttyS0\0"						\
-	"setbootargs=setenv bootargs "					\
-		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
-	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
-							"$netdev:off " \
-		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv rootdev /dev/nfs;"					\
-	"run setbootargs;"						\
-	"run setipargs;"						\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv rootdev /dev/ram;"					\
-	"run setbootargs;"						\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
deleted file mode 100644
index 98e9072..0000000
--- a/include/configs/MPC8315ERDB.h
+++ /dev/null
@@ -1,659 +0,0 @@
-/*
- * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFE000000
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC831x		1 /* MPC831x CPU family */
-#define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
-#define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_3X1)
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LALE_NORMAL)
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-		       HRCWH_FROM_0XFFF00100 |\
-		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
-		       HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-		       HRCWH_FROM_0X00000100 |\
-		       HRCWH_ROM_LOC_LOCAL_16BIT |\
-		       HRCWH_RL_EXT_LEGACY)
-#endif
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH		0x00000000
-#define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-#define CONFIG_HWCONFIG
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
-				| DDRCDR_PZ_LOZ \
-				| DDRCDR_NZ_LOZ \
-				| DDRCDR_ODT \
-				| DDRCDR_Q_DRN)
-				/* 0x7b880001 */
-/*
- * Manually set up DDR parameters
- * consist of two chips HY5PS12621BFP-C4 from HYNIX
- */
-#define CONFIG_SYS_DDR_SIZE		128 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-				| CSCONFIG_ODT_RD_NEVER \
-				| CSCONFIG_ODT_WR_ONLY_CURRENT \
-				| CSCONFIG_ROW_BIT_13 \
-				| CSCONFIG_COL_BIT_10)
-				/* 0x80010102 */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
-				| (0 << TIMING_CFG0_WRT_SHIFT) \
-				| (0 << TIMING_CFG0_RRT_SHIFT) \
-				| (0 << TIMING_CFG0_WWT_SHIFT) \
-				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
-				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
-				/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
-				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
-				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
-				| (6 << TIMING_CFG1_REFREC_SHIFT) \
-				| (2 << TIMING_CFG1_WRREC_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
-				| (2 << TIMING_CFG1_WRTORD_SHIFT))
-				/* 0x27256222 */
-#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
-				| (4 << TIMING_CFG2_CPO_SHIFT) \
-				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
-				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
-				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
-				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
-				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
-				/* 0x121048c5 */
-#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
-				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
-				/* 0x03600100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
-				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_DBW_32)
-				/* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
-				| (0x0232 << SDRAM_MODE_SD_SHIFT))
-				/* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2	0x00000000
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00140000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR		0x00040000
-#define CONFIG_FSL_ELBC		1
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
-
-					/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
-					| BR_PS_16	/* 16 bit port */ \
-					| BR_MS_GPCM	/* MSEL = GPCM */ \
-					| BR_V)		/* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-					| OR_UPM_XAM \
-					| OR_GPCM_CSNT \
-					| OR_GPCM_ACS_DIV2 \
-					| OR_GPCM_XACS \
-					| OR_GPCM_SCY_15 \
-					| OR_GPCM_TRLX_SET \
-					| OR_GPCM_EHTR_SET \
-					| OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
-/* 127 64KB sectors and 8 8KB top sectors per device */
-#define CONFIG_SYS_MAX_FLASH_SECT	135
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE		0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE		0xE0600000
-#endif
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITION
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT			"nand0=e0600000.flash"
-#define MTDPARTS_DEFAULT		\
-	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
-
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_MTD_NAND_VERIFY_WRITE	1
-#define CONFIG_CMD_NAND			1
-#define CONFIG_NAND_FSL_ELBC		1
-#define CONFIG_SYS_NAND_BLOCK_SIZE	16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-
-#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
-				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
-				| BR_PS_8		/* 8 bit port */ \
-				| BR_MS_FCM		/* MSEL = FCM */ \
-				| BR_V)			/* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM	\
-				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
-				| OR_FCM_CSCT \
-				| OR_FCM_CST \
-				| OR_FCM_CHT \
-				| OR_FCM_SCY_1 \
-				| OR_FCM_TRLX \
-				| OR_FCM_EHTR)
-				/* 0xFFFF8396 */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
-	!defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
-
-/*
- * Board info - revision and where boot from
- */
-#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
-
-#define CONFIG_SYS_PCIE1_BASE		0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
-
-#define CONFIG_SYS_PCIE2_BASE		0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE
-
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-
-#define CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
-
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_SYS_SCCR_USBDRCM		3
-
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_PHY_TYPE	"utmi"
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET	0x25000
-#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_MII		1 /* MII PHY management */
-#define CONFIG_TSEC1		1
-#define CONFIG_TSEC1_NAME	"eTSEC0"
-#define CONFIG_TSEC2		1
-#define CONFIG_TSEC2_NAME	"eTSEC1"
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#define TSEC2_FLAGS		TSEC_GIGABIT
-
-/* Options are: eTSEC[0-1] */
-#define CONFIG_ETHPRIME		"eTSEC1"
-
-/*
- * SATA
- */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET	0x18000
-#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET	0x19000
-#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * Environment
- */
-#if !defined(CONFIG_SYS_RAMBOOT)
-	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		\
-			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
-	#define CONFIG_ENV_SIZE		0x2000
-#else
-	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
-	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-	#define CONFIG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PCI
-
-#if defined(CONFIG_SYS_RAMBOOT)
-    #undef CONFIG_CMD_SAVEENV
-    #undef CONFIG_CMD_LOADS
-#endif
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
-
-#undef CONFIG_WATCHDOG		/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
-	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
-#endif
-
-				/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-				/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE | \
-				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2		HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
-				| BATU_BL_128M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
-				| BATU_BL_8M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
-				| BATU_BL_32M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
-				| BATU_BL_128K \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-
-#define CONFIG_SYS_IBAT6L	0
-#define CONFIG_SYS_IBAT6U	0
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L	0
-#define CONFIG_SYS_IBAT7U	0
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consoledev=ttyS0\0"						\
-	"ramdiskaddr=1000000\0"						\
-	"ramdiskfile=ramfs.83xx\0"					\
-	"fdtaddr=780000\0"						\
-	"fdtfile=mpc8315erdb.dtb\0"					\
-	"usb_phy_type=utmi\0"						\
-	""
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-		"nfsroot=$serverip:$rootpath "				\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
-							"$netdev:off "	\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
deleted file mode 100644
index 65a63e2..0000000
--- a/include/configs/MPC8323ERDB.h
+++ /dev/null
@@ -1,555 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 family */
-#define CONFIG_QE		1	/* Has QE */
-#define CONFIG_MPC832x		1	/* MPC832x CPU specific */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-
-#define CONFIG_PCI		1
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN	66666667	/* in Hz */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_2_5X1 |\
-	HRCWL_CE_PLL_VCO_DIV_2 |\
-	HRCWL_CE_PLL_DIV_1X1 |\
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LALE_NORMAL)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL		0x00000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
-/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
-#define CONFIG_SYS_SPCR_OPT	1
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-
-#undef CONFIG_SPD_EEPROM
-#if defined(CONFIG_SPD_EEPROM)
-/* Determine DDR configuration from I2C interface
- */
-#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
-#else
-/* Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE	64	/* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-				| CSCONFIG_ROW_BIT_13 \
-				| CSCONFIG_COL_BIT_9)
-				/* 0x80010101 */
-#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
-				| (0 << TIMING_CFG0_WRT_SHIFT) \
-				| (0 << TIMING_CFG0_RRT_SHIFT) \
-				| (0 << TIMING_CFG0_WWT_SHIFT) \
-				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
-				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
-				/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
-				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
-				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
-				| (3 << TIMING_CFG1_REFREC_SHIFT) \
-				| (2 << TIMING_CFG1_WRREC_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
-				| (2 << TIMING_CFG1_WRTORD_SHIFT))
-				/* 0x26253222 */
-#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
-				| (31 << TIMING_CFG2_CPO_SHIFT) \
-				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
-				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
-				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
-				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
-				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
-				/* 0x1f9048c7 */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-				/* 0x02000000 */
-#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
-				| (0x0232 << SDRAM_MODE_SD_SHIFT))
-				/* 0x44480232 */
-#define CONFIG_SYS_DDR_MODE2	0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
-				| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
-				/* 0x03200064 */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
-				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_32_BE)
-				/* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START	0x00030000	/* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef  CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR		0x00000000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
-
-					/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16	/* 16 bit port */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_GPCM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-				/* 0xFE006FF7 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
-
-/*
- * Config on-board EEPROM
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
-#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
-#define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
-
-#endif	/* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME		"UEC0"
-
-#define CONFIG_UEC_ETH1		/* ETH3 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
-#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
-#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR	4
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
-#endif
-
-#define CONFIG_UEC_ETH2		/* ETH4 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
-#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
-#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR	0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
-#endif
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		\
-			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-	#define CONFIG_ENV_SECT_SIZE	0x20000
-	#define CONFIG_ENV_SIZE		0x2000
-#else
-	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
-	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-	#define CONFIG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ASKENV
-
-#if defined(CONFIG_PCI)
-	#define CONFIG_CMD_PCI
-#endif
-#if defined(CONFIG_SYS_RAMBOOT)
-	#undef CONFIG_CMD_SAVEENV
-	#undef CONFIG_CMD_LOADS
-#endif
-
-#undef CONFIG_WATCHDOG		/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#if (CONFIG_CMD_KGDB)
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-				/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-				/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-					/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2		HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
-				| BATU_BL_4M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
-				| BATU_BL_32M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L	(0)
-#define CONFIG_SYS_IBAT3U	(0)
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR \
-				| BATU_BL_128K \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_MEM_PHYS \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_MEM_PHYS \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MMIO_PHYS \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MMIO_PHYS \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#else
-#define CONFIG_SYS_IBAT5L	(0)
-#define CONFIG_SYS_IBAT5U	(0)
-#define CONFIG_SYS_IBAT6L	(0)
-#define CONFIG_SYS_IBAT6U	(0)
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#endif
-
-/* Nothing in BAT7 */
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-#if (CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_HAS_ETH0		/* add support for "ethaddr" */
-#define CONFIG_HAS_ETH1		/* add support for "eth1addr" */
-
-/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
- * (see CONFIG_SYS_I2C_EEPROM) */
-					/* MAC address offset in I2C EEPROM */
-#define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00
-
-#define CONFIG_NETDEV		"eth1"
-
-#define CONFIG_HOSTNAME		mpc8323erdb
-#define CONFIG_ROOTPATH		"/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-				/* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH	"u-boot.bin"
-#define CONFIG_FDTFILE		"mpc832x_rdb.dtb"
-#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
-
-				/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		800000
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"netdev=" CONFIG_NETDEV "\0"					\
-	"uboot=" CONFIG_UBOOTPATH "\0"					\
-	"tftpflash=tftp $loadaddr $uboot;"				\
-		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" +$filesize; "	\
-		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize; "	\
-		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize\0"	\
-	"fdtaddr=780000\0"						\
-	"fdtfile=" CONFIG_FDTFILE "\0"					\
-	"ramdiskaddr=1000000\0"						\
-	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
-	"console=ttyS0\0"						\
-	"setbootargs=setenv bootargs "					\
-		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
-	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
-								"$netdev:off "\
-		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv rootdev /dev/nfs;"					\
-	"run setbootargs;"						\
-	"run setipargs;"						\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv rootdev /dev/ram;"					\
-	"run setbootargs;"						\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
deleted file mode 100644
index 1735b3c..0000000
--- a/include/configs/MPC832XEMDS.h
+++ /dev/null
@@ -1,624 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 family */
-#define CONFIG_QE		1	/* Has QE */
-#define CONFIG_MPC832x		1	/* MPC832x CPU specific */
-#define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK	66000000	/* in HZ */
-#else
-#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	66000000
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_2X1 |\
-	HRCWL_CE_PLL_VCO_DIV_2 |\
-	HRCWL_CE_PLL_DIV_1X1 |\
-	HRCWL_CE_TO_PLL_1X3)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT |\
-	HRCWH_PCI1_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LALE_NORMAL)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LALE_NORMAL)
-#endif
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL		0x00000000
-
-#define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDRCDR	0x73000002	/* DDR II voltage is 1.8V */
-
-#undef CONFIG_SPD_EEPROM
-#if defined(CONFIG_SPD_EEPROM)
-/* Determine DDR configuration from I2C interface
- */
-#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
-#else
-/* Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE		128	/* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-					| CSCONFIG_AP \
-					| CSCONFIG_ODT_WR_CFG \
-					| CSCONFIG_ROW_BIT_13 \
-					| CSCONFIG_COL_BIT_10)
-					/* 0x80840102 */
-#define CONFIG_SYS_DDR_TIMING_0		((0 << TIMING_CFG0_RWT_SHIFT) \
-					| (0 << TIMING_CFG0_WRT_SHIFT) \
-					| (0 << TIMING_CFG0_RRT_SHIFT) \
-					| (0 << TIMING_CFG0_WWT_SHIFT) \
-					| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
-					| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
-					| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
-					| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
-					/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1		((3 << TIMING_CFG1_PRETOACT_SHIFT) \
-					| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
-					| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
-					| (5 << TIMING_CFG1_CASLAT_SHIFT) \
-					| (13 << TIMING_CFG1_REFREC_SHIFT) \
-					| (3 << TIMING_CFG1_WRREC_SHIFT) \
-					| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
-					| (2 << TIMING_CFG1_WRTORD_SHIFT))
-					/* 0x3935D322 */
-#define CONFIG_SYS_DDR_TIMING_2		((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
-				| (31 << TIMING_CFG2_CPO_SHIFT) \
-				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
-				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
-				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
-				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
-				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
-				/* 0x0F9048CA */
-#define CONFIG_SYS_DDR_TIMING_3		0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-					/* 0x02000000 */
-#define CONFIG_SYS_DDR_MODE		((0x4440 << SDRAM_MODE_ESD_SHIFT) \
-					| (0x0232 << SDRAM_MODE_SD_SHIFT))
-					/* 0x44400232 */
-#define CONFIG_SYS_DDR_MODE2		0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL		((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
-					| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
-					/* 0x03200064 */
-#define CONFIG_SYS_DDR_CS0_BNDS		0x00000007
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
-					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-					| SDRAM_CFG_32_BE)
-					/* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00100000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef  CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR		0x00000000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE	16	/* FLASH size is 16M */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
-
-					/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16	/* 16 bit port */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_GPCM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-				/* 0xfe006ff7 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * BCSR on the Local Bus
- */
-#define CONFIG_SYS_BCSR			0xF8000000
-					/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR \
-					| BR_PS_8 \
-					| BR_MS_GPCM \
-					| BR_V)
-#define CONFIG_SYS_OR1_PRELIM		(OR_AM_32KB \
-					| OR_GPCM_XAM \
-					| OR_GPCM_CSNT \
-					| OR_GPCM_XACS \
-					| OR_GPCM_SCY_15 \
-					| OR_GPCM_TRLX_SET \
-					| OR_GPCM_EHTR_SET \
-					| OR_GPCM_EAD)
-					/* 0xFFFFE9F7 */
-
-/*
- * Windows to access PIB via local bus
- */
-					/* PIB window base 0xF8008000 */
-#define CONFIG_SYS_PIB_BASE		0xF8008000
-#define CONFIG_SYS_PIB_WINDOW_SIZE	(32 * 1024)
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PIB_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
-
-/*
- * CS2 on Local Bus, to PIB
- */
-#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_PIB_BASE \
-				| BR_PS_8 \
-				| BR_MS_GPCM \
-				| BR_V)
-				/* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
-				| OR_GPCM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-				/* 0xffffe9f7 */
-
-/*
- * CS3 on Local Bus, to PIB
- */
-#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_PIB_BASE + \
-					CONFIG_SYS_PIB_WINDOW_SIZE) \
-				| BR_PS_8 \
-				| BR_MS_GPCM \
-				| BR_V)
-				/* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
-				| OR_GPCM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-				/* 0xffffe9f7 */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE		0x100000	/* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
-
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CONFIG_83XX_PCI_STREAMING
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
-
-#endif	/* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME		"UEC0"
-
-#define CONFIG_UEC_ETH1		/* ETH3 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
-#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
-#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR	3
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
-#endif
-
-#define CONFIG_UEC_ETH2		/* ETH4 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM	3	/* UCC4 */
-#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK7
-#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
-#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR	4
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
-#endif
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		\
-			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-	#define CONFIG_ENV_SECT_SIZE	0x20000
-	#define CONFIG_ENV_SIZE		0x2000
-#else
-	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
-	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-	#define CONFIG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_ASKENV
-
-#if defined(CONFIG_PCI)
-    #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-    #undef CONFIG_CMD_SAVEENV
-    #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG		/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-				/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-				/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-					/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2		HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
-				| BATU_BL_4M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR \
-				| BATU_BL_128K \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE \
-				| BATU_BL_32M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L	(0)
-#define CONFIG_SYS_IBAT4U	(0)
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
-				| BATU_BL_128K \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L	(0)
-#define CONFIG_SYS_IBAT6U	(0)
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */ #define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE	115200
-
-#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
-#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consoledev=ttyS0\0"						\
-	"ramdiskaddr=1000000\0"						\
-	"ramdiskfile=ramfs.83xx\0"					\
-	"fdtaddr=780000\0"						\
-	"fdtfile=mpc832x_mds.dtb\0"					\
-	""
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-		"nfsroot=$serverip:$rootpath "				\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
-							"$netdev:off "	\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
deleted file mode 100644
index 6b7d648..0000000
--- a/include/configs/MPC8349EMDS.h
+++ /dev/null
@@ -1,810 +0,0 @@
-/*
- * (C) Copyright 2006-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mpc8349emds board configuration file
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC834x		1	/* MPC834x family */
-#define CONFIG_MPC8349		1	/* MPC8349 specific */
-#define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
-#else
-#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_PCI
-#define CONFIG_83XX_PCICLK	66666666	/* in Hz */
-#endif /* CONFIG_PCISLAVE */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ	66000000
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define CONFIG_SYS_CLK_FREQ	33000000
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
-#endif
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
-
-#define CONFIG_SYS_IMMR		0xE0000000
-
-#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START	0x00000000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00100000
-
-/*
- * DDR Setup
- */
-#define CONFIG_DDR_ECC			/* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
-
-/*
- * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
- * undefine it to use old spd_sdram.c
- */
-#define CONFIG_SYS_FSL_DDR2
-#ifdef CONFIG_SYS_FSL_DDR2
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#define SPD_EEPROM_ADDRESS1	0x52
-#define SPD_EEPROM_ADDRESS2	0x51
-#define CONFIG_NUM_DDR_CONTROLLERS	1
-#define CONFIG_DIMM_SLOTS_PER_CTLR	2
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-#endif
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
-					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#undef  CONFIG_DDR_2T_TIMING
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
-
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
-#else
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR		0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
-#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
-#define CONFIG_SYS_DDR_TIMING_0		0x00220802
-#define CONFIG_SYS_DDR_TIMING_1		0x38357322
-#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3		0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
-#define CONFIG_SYS_DDR_MODE		0x47d00432
-#define CONFIG_SYS_DDR_MODE2		0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#else
-#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
-				| CSCONFIG_ROW_BIT_13 \
-				| CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_TIMING_1	0x36332321
-#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
-#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
-
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
-				/* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE	0x00000023
-#else
-/* the default burst length is 4 - for 64-bit data path */
-				/* DLL,normal,seq,4/2.5, 4 burst len */
-#define CONFIG_SYS_DDR_MODE	0x00000022
-#endif
-#endif
-#endif
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE		32	/* max flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16	/* 16 bit port  */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_UPM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-
-					/* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef  CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
- */
-#define CONFIG_SYS_BCSR			0xE2400000
-					/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR \
-					| BR_PS_8 \
-					| BR_MS_GPCM \
-					| BR_V)
-					/* 0x00000801 */
-#define CONFIG_SYS_OR1_PRELIM		(OR_AM_32KB \
-					| OR_GPCM_XAM \
-					| OR_GPCM_CSNT \
-					| OR_GPCM_SCY_15 \
-					| OR_GPCM_TRLX_CLEAR \
-					| OR_GPCM_EHTR_CLEAR)
-					/* 0xFFFFE8F0 */
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
-/*
- * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
- * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
- */
-#undef CONFIG_SYS_LB_SDRAM
-
-#ifdef CONFIG_SYS_LB_SDRAM
-/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- *    port-size = 32-bits = BR2[19:20] = 11
- *    no parity checking = BR2[21:22] = 00
- *    SDRAM for MSEL = BR2[24:26] = 011
- *    Valid = BR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LBC_SDRAM_BASE \
-					| BR_PS_32	/* 32-bit port */ \
-					| BR_MS_SDRAM	/* MSEL = SDRAM */ \
-					| BR_V)		/* Valid */
-					/* 0xF0001861 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- *    64MB mask for AM, OR2[0:7] = 1111 1100
- *                 XAM, OR2[17:18] = 11
- *    9 columns OR2[19-21] = 010
- *    13 rows   OR2[23-25] = 100
- *    EAD set for extra time OR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM	(OR_AM_64MB \
-			| OR_SDRAM_XAM \
-			| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
-			| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
-			| OR_SDRAM_EAD)
-			/* 0xFC006901 */
-
-				/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT	0x32000000
-				/* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR	0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN	\
-				| LSDMR_BSMA1516	\
-				| LSDMR_RFCR8		\
-				| LSDMR_PRETOACT6	\
-				| LSDMR_ACTTORW3	\
-				| LSDMR_BL8		\
-				| LSDMR_WRC3		\
-				| LSDMR_CL3)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX     1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/* SPI */
-#define CONFIG_MPC8XXX_SPI
-#undef CONFIG_SOFT_SPI			/* SPI bit-banged */
-
-/* GPIOs.  Used as SPI chip selects */
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
-#define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/* USB */
-#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CONFIG_83XX_PCI_STREAMING
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#if !defined(CONFIG_PCI_PNP)
-	#define PCI_ENET0_IOADDR	0xFIXME
-	#define PCI_ENET0_MEMADDR	0xFIXME
-	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
-
-#endif	/* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_GMII		1	/* MII PHY management */
-#define CONFIG_TSEC1		1
-#define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_TSEC2		1
-#define CONFIG_TSEC2_NAME	"TSEC1"
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#define TSEC2_FLAGS		TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME		"TSEC0"
-
-#endif	/* CONFIG_TSEC_ENET */
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		\
-			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
-	#define CONFIG_ENV_SIZE		0x2000
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#else
-	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
-	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-	#define CONFIG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-
-#if defined(CONFIG_PCI)
-    #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-    #undef CONFIG_CMD_SAVEENV
-    #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-				/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-				/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-				/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
-
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_DISABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif /* PCI_64BIT */
-#endif /* CONFIG_PCISLAVE */
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
-#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
-				| HID0_ENABLE_INSTRUCTION_CACHE)
-
-/* #define CONFIG_SYS_HID0_FINAL	(\
-	HID0_ENABLE_INSTRUCTION_CACHE |\
-	HID0_ENABLE_M_BIT |\
-	HID0_ENABLE_ADDRESS_BROADCAST) */
-
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* PCI @ 0x80000000 */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L	(0)
-#define CONFIG_SYS_IBAT1U	(0)
-#define CONFIG_SYS_IBAT2L	(0)
-#define CONFIG_SYS_IBAT2U	(0)
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L	(0)
-#define CONFIG_SYS_IBAT3U	(0)
-#define CONFIG_SYS_IBAT4L	(0)
-#define CONFIG_SYS_IBAT4U	(0)
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L	(0xF0000000 \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U	(0xF0000000 \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
-#endif
-
-#define CONFIG_HOSTNAME		mpc8349emds
-#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
-#define CONFIG_BOOTFILE		"uImage"
-
-#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
-#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE	 115200
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=mpc8349emds\0"					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
-		"bootm\0"						\
-	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
-	"update=protect off fe000000 fe03ffff; "			\
-		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
-	"upd=run load update\0"						\
-	"fdtaddr=780000\0"						\
-	"fdtfile=mpc834x_mds.dtb\0"					\
-	""
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-		"nfsroot=$serverip:$rootpath "				\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
-							"$netdev:off "	\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
deleted file mode 100644
index 398918a..0000000
--- a/include/configs/MPC8349ITX.h
+++ /dev/null
@@ -1,806 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
-
- Memory map:
-
- 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
- 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
- 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
- 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
- 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
- 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
- 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
- 0xF001_0000-0xF001_FFFF Local bus expansion slot
- 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
- 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
- 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
-
- I2C address list:
-						Align.	Board
- Bus	Addr	Part No.	Description	Length	Location
- ----------------------------------------------------------------
- I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64
-
- I2C1	0x20	PCF8574		I2C Expander	0	U8
- I2C1	0x21	PCF8574		I2C Expander	0	U10
- I2C1	0x38	PCF8574A	I2C Expander	0	U8
- I2C1	0x39	PCF8574A	I2C Expander	0	U10
- I2C1	0x51	(DDR)		DDR EEPROM	1	U1
- I2C1	0x68	DS1339		RTC		1	U68
-
- Note that a given board has *either* a pair of 8574s or a pair of 8574As.
-*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
-#define CONFIG_SYS_LOWBOOT
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC834x		/* MPC834x family (8343, 8347, 8349) */
-#define CONFIG_MPC8349		/* MPC8349 specific */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFEF00000
-#endif
-
-#define CONFIG_SYS_IMMR	0xE0000000	/* The IMMR is relocated to here */
-
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- */
-
-#ifdef CONFIG_MPC8349ITX
-/* The CF card interface on the back of the board */
-#define CONFIG_COMPACT_FLASH
-#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
-#define CONFIG_SATA_SIL3114	/* SIL3114 SATA controller */
-#define CONFIG_SYS_USB_HOST	/* use the EHCI USB controller */
-#endif
-
-#define CONFIG_PCI
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C
-#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
-
-/*
- * Device configurations
- */
-
-/* I2C */
-#ifdef CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-
-#define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
-#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC */
-
-#define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
-#define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
-#define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
-#define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* I2C1, DS1339 RTC*/
-#define SPD_EEPROM_ADDRESS		0x51	/* I2C1, DDR */
-
-/* Don't probe these addresses: */
-#define CONFIG_SYS_I2C_NOPROBES	{ {1, CONFIG_SYS_I2C_8574_ADDR1}, \
-				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
-				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
-				 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
-/* Bit definitions for the 8574[A] I2C expander */
-				/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
-#define I2C_8574_REVISION	0x03
-#define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
-#define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
-#define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
-#define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/
-
-#endif
-
-/* Compact Flash */
-#ifdef CONFIG_COMPACT_FLASH
-
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
-#define CONFIG_SYS_ATA_REG_OFFSET	0
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
-#define CONFIG_SYS_ATA_STRIDE		2
-
-/* If a CF card is not inserted, time out quickly */
-#define ATA_RESET_TIME	1
-
-#endif
-
-/*
- * SATA
- */
-#ifdef CONFIG_SATA_SIL3114
-
-#define CONFIG_SYS_SATA_MAX_DEVICE      4
-#define CONFIG_LIBATA
-#define CONFIG_LBA48
-
-#endif
-
-#ifdef CONFIG_SYS_USB_HOST
-/*
- * Support USB
- */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-
-/* Current USB implementation supports the only USB controller,
- * so we have to choose between the MPH or the DR ones */
-#if 1
-#define CONFIG_HAS_FSL_MPH_USB
-#else
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-#define CONFIG_SYS_MEMTEST_START	0x1000	/* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x2000
-
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
-					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
-
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
-
-#ifdef CONFIG_SYS_I2C
-#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
-#endif
-
-/* No SPD? Then manually set up DDR parameters */
-#ifndef CONFIG_SPD_EEPROM
-    #define CONFIG_SYS_DDR_SIZE		256	/* Mb */
-    #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-					| CSCONFIG_ROW_BIT_13 \
-					| CSCONFIG_COL_BIT_10)
-
-    #define CONFIG_SYS_DDR_TIMING_1	0x26242321
-    #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
-#endif
-
-/*
- *Flash on the Local Bus
- */
-
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-/* 127 64KB sectors + 8 8KB sectors per device */
-#define CONFIG_SYS_MAX_FLASH_SECT	135
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
-boards, we say we have two, but don't display a message if we find only one. */
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	\
-		{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
-#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC2
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE		0xFEFFE000
-#define CONFIG_VSC7385_IMAGE_SIZE	8192
-
-#endif
-
-/*
- * BRx, ORx, LBLAWBARx, and LBLAWARx
- */
-
-/* Flash */
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16 \
-				| BR_MS_GPCM \
-				| BR_V)
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_UPM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_16MB)
-
-/* Vitesse 7385 */
-
-#define CONFIG_SYS_VSC7385_BASE	0xF8000000
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_VSC7385_BASE \
-				| BR_PS_8 \
-				| BR_MS_GPCM \
-				| BR_V)
-#define CONFIG_SYS_OR1_PRELIM	(OR_AM_128KB \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_SETA \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
-
-#endif
-
-/* LED */
-
-#define CONFIG_SYS_LED_BASE	0xF9000000
-#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_LED_BASE \
-				| BR_PS_8 \
-				| BR_MS_GPCM \
-				| BR_V)
-#define CONFIG_SYS_OR2_PRELIM	(OR_AM_2MB \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_9 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-
-/* Compact Flash */
-
-#ifdef CONFIG_COMPACT_FLASH
-
-#define CONFIG_SYS_CF_BASE	0xF0000000
-
-#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_CF_BASE \
-				| BR_PS_16 \
-				| BR_MS_UPMA \
-				| BR_V)
-#define CONFIG_SYS_OR3_PRELIM	(OR_UPM_AM | OR_UPM_BI)
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CF_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
-
-#endif
-
-/*
- * U-Boot memory configuration
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
-				/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT	0x32000000
-				/* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR	0x20000000
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_CONSOLE		ttyS0
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
- * PCI
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_MPC83XX_PCI2
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE	\
-			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE		0x01000000	/* 16M */
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE	\
-			(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE	\
-			(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS		\
-			(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE		0x01000000	/* 16M */
-#endif
-
-#define CONFIG_PCI_PNP			/* do pci plug-and-play */
-
-#ifndef CONFIG_PCI_PNP
-    #define PCI_ENET0_IOADDR	0x00000000
-    #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
-    #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#endif
-
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN	66666666	/* in Hz */
-#else
-#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
-#endif
-
-/* TSEC */
-
-#ifdef CONFIG_TSEC_ENET
-
-#define CONFIG_MII
-#define CONFIG_PHY_GIGE		/* In case CONFIG_CMD_MII is specified */
-
-#define CONFIG_TSEC1
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME  "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
-#define TSEC1_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME  "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET	0x25000
-
-#define TSEC2_PHY_ADDR		4
-#define TSEC2_PHYIDX		0
-#define TSEC2_FLAGS		TSEC_GIGABIT
-#endif
-
-#define CONFIG_ETHPRIME		"Freescale TSEC"
-
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_ENV_OVERWRITE
-
-#ifndef CONFIG_SYS_RAMBOOT
-  #define CONFIG_ENV_IS_IN_FLASH
-  #define CONFIG_ENV_ADDR	\
-			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-  #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
-  #define CONFIG_ENV_SIZE	0x2000
-#else
-  #define CONFIG_SYS_NO_FLASH	/* Flash is not usable now */
-  #undef  CONFIG_FLASH_CFI_DRIVER
-  #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
-  #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - 0x1000)
-  #define CONFIG_ENV_SIZE	0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-
-#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
-				|| defined(CONFIG_USB_STORAGE)
-	#define CONFIG_DOS_PARTITION
-	#define CONFIG_CMD_FAT
-	#define CONFIG_SUPPORT_VFAT
-#endif
-
-#ifdef CONFIG_COMPACT_FLASH
-	#define CONFIG_CMD_IDE
-#endif
-
-#ifdef CONFIG_SATA_SIL3114
-	#define CONFIG_CMD_SATA
-#endif
-
-#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
-	#define CONFIG_CMD_EXT2
-#endif
-
-#ifdef CONFIG_PCI
-	#define CONFIG_CMD_PCI
-#endif
-
-#ifdef CONFIG_SYS_I2C
-	#define CONFIG_CMD_I2C
-#endif
-
-/* Watchdog */
-#undef CONFIG_WATCHDOG		/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser */
-
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
-
-#ifdef CONFIG_MPC8349ITX
-#define CONFIG_SYS_PROMPT "MPC8349E-mITX> "	/* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-				/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-				/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-				/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
-#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_USBMPHCM 3	/* USB MPH controller's clock */
-#define CONFIG_SYS_SCCR_USBDRCM	0	/* USB DR controller's clock */
-
-/*
- * System IO Config
- */
-/* Needed for gigabit to work on TSEC 1 */
-#define CONFIG_SYS_SICRH SICRH_TSOBI1
-				/* USB DR as device + USB MPH as host */
-#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1)
-
-#define CONFIG_SYS_HID0_INIT	0x00000000
-#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_INSTRUCTION_CACHE
-
-#define CONFIG_SYS_HID2	HID2_HBE
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* DDR  */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* PCI  */
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L	0
-#define CONFIG_SYS_IBAT1U	0
-#define CONFIG_SYS_IBAT2L	0
-#define CONFIG_SYS_IBAT2U	0
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L	0
-#define CONFIG_SYS_IBAT3U	0
-#define CONFIG_SYS_IBAT4L	0
-#define CONFIG_SYS_IBAT4U	0
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L	(0xF0000000 \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U	(0xF0000000 \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-#define CONFIG_SYS_IBAT7L	0
-#define CONFIG_SYS_IBAT7U	0
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV		"eth0"
-
-#ifdef CONFIG_MPC8349ITX
-#define CONFIG_HOSTNAME		"mpc8349emitx"
-#else
-#define CONFIG_HOSTNAME		"mpc8349emitxgp"
-#endif
-
-/* Default path and filenames */
-#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
-#define CONFIG_BOOTFILE		"uImage"
-				/* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH	"u-boot.bin"
-
-#ifdef CONFIG_MPC8349ITX
-#define CONFIG_FDTFILE		"mpc8349emitx.dtb"
-#else
-#define CONFIG_FDTFILE		"mpc8349emitxgp.dtb"
-#endif
-
-#define CONFIG_BOOTDELAY	6
-
-#define CONFIG_BOOTARGS \
-	"root=/dev/nfs rw" \
-	" nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH	\
-	" ip=" __stringify(CONFIG_IPADDR) ":"		\
-		__stringify(CONFIG_SERVERIP) ":"	\
-		__stringify(CONFIG_GATEWAYIP) ":"	\
-		__stringify(CONFIG_NETMASK) ":"		\
-		CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off"		\
-	" console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"console=" __stringify(CONFIG_CONSOLE) "\0"			\
-	"netdev=" CONFIG_NETDEV "\0"					\
-	"uboot=" CONFIG_UBOOTPATH "\0"					\
-	"tftpflash=tftpboot $loadaddr $uboot; "				\
-		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" +$filesize; "	\
-		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize; "	\
-		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize\0"	\
-	"fdtaddr=780000\0"						\
-	"fdtfile=" CONFIG_FDTFILE "\0"
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
-	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
-	" console=$console,$baudrate $othbootargs; "			\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw"				\
-	" console=$console,$baudrate $othbootargs; "			\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
deleted file mode 100644
index 832c10f..0000000
--- a/include/configs/MPC837XEMDS.h
+++ /dev/null
@@ -1,719 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC837x		1 /* MPC837x CPU specific */
-#define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	66000000
-#endif
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66MHz, then
- * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_6X1 |\
-	HRCWL_CORE_TO_CSB_1_5X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT |\
-	HRCWH_PCI1_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LDP_CLEAR)
-#endif
-
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count is 4 */
-
-/* System Priority Control Register */
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC1/2 emergency has highest priority */
-
-/*
- * IP blocks clock configuration
- */
-#define CONFIG_SYS_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
-#define CONFIG_SYS_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
-#define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH		0x00000000
-#define CONFIG_SYS_SICRL		0x00000000
-
-/*
- * Output Buffer Impedance
- */
-#define CONFIG_SYS_OBIR		0x31100000
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_HWCONFIG
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-#define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_DHC_EN \
-					| DDRCDR_ODT \
-					| DDRCDR_Q_DRN)
-					/* 0x80080001 */ /* ODT 150ohm on SoC */
-
-#undef CONFIG_DDR_ECC		/* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
-
-#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
-#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
-
-#if defined(CONFIG_SPD_EEPROM)
-#define SPD_EEPROM_ADDRESS	0x51 /* I2C address of DDR SODIMM SPD */
-#else
-/*
- * Manually set up DDR parameters
- * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
- * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
- */
-#define CONFIG_SYS_DDR_SIZE		512 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001f
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-			| CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
-			| CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
-			| CSCONFIG_ROW_BIT_14 \
-			| CSCONFIG_COL_BIT_10)
-			/* 0x80010202 */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
-				| (0 << TIMING_CFG0_WRT_SHIFT) \
-				| (0 << TIMING_CFG0_RRT_SHIFT) \
-				| (0 << TIMING_CFG0_WWT_SHIFT) \
-				| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
-				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
-				/* 0x00620802 */
-#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
-				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
-				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
-				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
-				| (13 << TIMING_CFG1_REFREC_SHIFT) \
-				| (3 << TIMING_CFG1_WRREC_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
-				| (2 << TIMING_CFG1_WRTORD_SHIFT))
-				/* 0x3935d322 */
-#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
-				| (6 << TIMING_CFG2_CPO_SHIFT) \
-				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
-				| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
-				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
-				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
-				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
-				/* 0x131088c8 */
-#define CONFIG_SYS_DDR_INTERVAL	((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
-				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
-				/* 0x03E00100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE	((0x0448 << SDRAM_MODE_ESD_SHIFT) \
-				| (0x1432 << SDRAM_MODE_SD_SHIFT))
-				/* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2	0x00000000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00140000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR		0x00000000
-#define CONFIG_FSL_ELBC		1
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI	/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE	0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE	32 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
-
-					/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16	/* 16 bit port */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_UPM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-				/* 0xFE000FF7 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
-
-/*
- * BCSR on the Local Bus
- */
-#define CONFIG_SYS_BCSR		0xF8000000
-					/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_BCSR \
-				| BR_PS_8 \
-				| BR_MS_GPCM \
-				| BR_V)
-				/* 0xF8000801 */
-#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
-				| OR_GPCM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-				/* 0xFFFFE9F7 */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_CMD_NAND		1
-#define CONFIG_MTD_NAND_VERIFY_WRITE	1
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_NAND_FSL_ELBC	1
-
-#define CONFIG_SYS_NAND_BASE	0xE0600000
-#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE \
-				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
-				| BR_PS_8		/* 8 bit port */ \
-				| BR_MS_FCM		/* MSEL = FCM */ \
-				| BR_V)			/* valid */
-#define CONFIG_SYS_OR3_PRELIM	(OR_AM_32KB \
-				| OR_FCM_BCTLD \
-				| OR_FCM_CST \
-				| OR_FCM_CHT \
-				| OR_FCM_SCY_1 \
-				| OR_FCM_RST \
-				| OR_FCM_TRLX \
-				| OR_FCM_EHTR)
-				/* 0xFFFF919E */
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
-
-#define CONFIG_SYS_PCIE1_BASE		0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
-
-#define CONFIG_SYS_PCIE2_BASE		0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#ifndef __ASSEMBLY__
-extern int board_pci_host_broken(void);
-#endif
-#define CONFIG_PCIE
-#define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
-
-#define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET	0x25000
-#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_MII		1 /* MII PHY management */
-#define CONFIG_TSEC1		1
-#define CONFIG_TSEC1_NAME	"eTSEC0"
-#define CONFIG_TSEC2		1
-#define CONFIG_TSEC2_NAME	"eTSEC1"
-#define TSEC1_PHY_ADDR		2
-#define TSEC2_PHY_ADDR		3
-#define TSEC1_PHY_ADDR_SGMII	8
-#define TSEC2_PHY_ADDR_SGMII	4
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME		"eTSEC1"
-
-/* SERDES */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1	0xe3000
-#define CONFIG_FSL_SERDES2	0xe3100
-
-/*
- * SATA
- */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET	0x18000
-#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET	0x19000
-#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		\
-			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
-	#define CONFIG_ENV_SIZE		0x2000
-#else
-	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
-	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-	#define CONFIG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-
-#if defined(CONFIG_PCI)
-    #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-    #undef CONFIG_CMD_SAVEENV
-    #undef CONFIG_CMD_LOADS
-#endif
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-
-#undef CONFIG_WATCHDOG		/* watchdog disabled */
-
-#define CONFIG_MMC     1
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
-	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
-#endif
-
-				/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-				/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2		HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
-
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR \
-				| BATU_BL_8M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_BCSR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_BCSR \
-				| BATU_BL_128K \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE \
-				| BATU_BL_32M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
-				| BATU_BL_128K \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L	(0)
-#define CONFIG_SYS_IBAT6U	(0)
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consoledev=ttyS0\0"						\
-	"ramdiskaddr=1000000\0"						\
-	"ramdiskfile=ramfs.83xx\0"					\
-	"fdtaddr=780000\0"						\
-	"fdtfile=mpc8379_mds.dtb\0"					\
-	""
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-		"nfsroot=$serverip:$rootpath "				\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
-							"$netdev:off "	\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif	/* __CONFIG_H */
