From patchwork Thu Mar 12 03:31:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Wang X-Patchwork-Id: 449290 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B66E314012F for ; Thu, 12 Mar 2015 14:35:06 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7DF0FA742E; Thu, 12 Mar 2015 04:35:03 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dc8E0NbxyIbt; Thu, 12 Mar 2015 04:35:03 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0062EA7429; Thu, 12 Mar 2015 04:35:03 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 38547A7429 for ; Thu, 12 Mar 2015 04:35:00 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DB1-73GTc6Xj for ; Thu, 12 Mar 2015 04:35:00 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1on0119.outbound.protection.outlook.com [157.56.110.119]) by theia.denx.de (Postfix) with ESMTPS id 4A6BDA7428 for ; Thu, 12 Mar 2015 04:34:55 +0100 (CET) Received: from BY2PR03CA065.namprd03.prod.outlook.com (10.141.249.38) by BY2PR03MB159.namprd03.prod.outlook.com (10.242.36.18) with Microsoft SMTP Server (TLS) id 15.1.99.9; Thu, 12 Mar 2015 03:34:52 +0000 Received: from BN1AFFO11FD013.protection.gbl (2a01:111:f400:7c10::169) by BY2PR03CA065.outlook.office365.com (2a01:111:e400:2c5d::38) with Microsoft SMTP Server (TLS) id 15.1.106.15 via Frontend Transport; Thu, 12 Mar 2015 03:34:52 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD013.mail.protection.outlook.com (10.58.52.73) with Microsoft SMTP Server (TLS) id 15.1.112.13 via Frontend Transport; Thu, 12 Mar 2015 03:34:52 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t2C3Ymhh004647; Wed, 11 Mar 2015 20:34:49 -0700 From: Alison Wang To: , , Date: Thu, 12 Mar 2015 11:31:55 +0800 Message-ID: <1426131115-43083-1-git-send-email-b18965@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=b18965@freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; BMV:0; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(189002)(199003)(107886001)(106466001)(77156002)(551934003)(33646002)(229853001)(104016003)(6806004)(19580395003)(85426001)(19580405001)(87936001)(77096005)(62966003)(46102003)(47776003)(2201001)(50986999)(105606002)(50226001)(48376002)(92566002)(36756003)(450100001)(50466002)(42262002); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR03MB159; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY2PR03MB159; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(5001009); SRVR:BY2PR03MB159; BCL:0; PCL:0; RULEID:; SRVR:BY2PR03MB159; X-Forefront-PRVS: 05134F8B4F X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2015 03:34:52.0544 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR03MB159 Subject: [U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of outstanding read transactions for slave interface S2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch will enable regulation of outstanding read transactions for slave interface S2 for silicon VER1.0. Signed-off-by: Alison Wang --- Changes in v2: - Modify the subject and commit to describe accurately arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++ board/freescale/ls1021aqds/ls1021aqds.c | 7 +++++++ board/freescale/ls1021atwr/ls1021atwr.c | 7 +++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index a8122c1..1766f88 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -499,6 +499,8 @@ struct ccsr_ddr { #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 #define CCI400_SNOOP_REQ_EN 0x00000001 +#define CCI400_REGULATION_READ_EN 0x00000008 +#define CCI400_INT_MAX_OUT_TRANS 0x01000000 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 69a5671..b7d1c90 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -225,6 +225,13 @@ int board_early_init_f(void) */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + /* + * To fix interleaving issue on VER1.0, regulation of + * outstanding read transactions for slave interface S2 + * is enabled + */ + out_le32(&cci->slave[2].qos_ctrl, CCI400_REGULATION_READ_EN); + out_le32(&cci->slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS); /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index a9c87f2..bba3073 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -309,6 +309,13 @@ int board_early_init_f(void) */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + /* + * To fix interleaving issue on VER1.0, regulation of + * outstanding read transactions for slave interface S2 + * is enabled + */ + out_le32(&cci->slave[2].qos_ctrl, CCI400_REGULATION_READ_EN); + out_le32(&cci->slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS); } return 0;