From patchwork Wed Mar 11 09:12:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Qiang X-Patchwork-Id: 448860 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1D33714016A for ; Wed, 11 Mar 2015 20:15:34 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3B2784A044; Wed, 11 Mar 2015 10:15:31 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vxxGNGoH4LqX; Wed, 11 Mar 2015 10:15:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 75D56A741B; Wed, 11 Mar 2015 10:15:30 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6720AA741B for ; Wed, 11 Mar 2015 10:15:27 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eGAUWYCSMjhk for ; Wed, 11 Mar 2015 10:15:27 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0114.outbound.protection.outlook.com [65.55.169.114]) by theia.denx.de (Postfix) with ESMTPS id 619604A039 for ; Wed, 11 Mar 2015 10:15:22 +0100 (CET) Received: from DM2PR03CA0030.namprd03.prod.outlook.com (10.141.96.29) by BLUPR03MB344.namprd03.prod.outlook.com (10.141.48.24) with Microsoft SMTP Server (TLS) id 15.1.106.11; Wed, 11 Mar 2015 09:15:20 +0000 Received: from BY2FFO11FD008.protection.gbl (2a01:111:f400:7c0c::176) by DM2PR03CA0030.outlook.office365.com (2a01:111:e400:2428::29) with Microsoft SMTP Server (TLS) id 15.1.106.15 via Frontend Transport; Wed, 11 Mar 2015 09:15:19 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD008.mail.protection.outlook.com (10.1.14.159) with Microsoft SMTP Server (TLS) id 15.1.112.13 via Frontend Transport; Wed, 11 Mar 2015 09:15:18 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t2B9FFLZ022658; Wed, 11 Mar 2015 02:15:16 -0700 From: Zhao Qiang To: , Date: Wed, 11 Mar 2015 17:12:17 +0800 Message-ID: <1426065137-1859-1-git-send-email-B45475@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=B45475@freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(189002)(199003)(77156002)(87936001)(19580395003)(92566002)(77096005)(450100001)(19580405001)(85426001)(47776003)(50226001)(104016003)(36756003)(105606002)(50466002)(46102003)(48376002)(229853001)(50986999)(106466001)(6806004)(42262002)(19627235001); DIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB344; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB344; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002009)(5005006); SRVR:BLUPR03MB344; BCL:0; PCL:0; RULEID:; SRVR:BLUPR03MB344; X-Forefront-PRVS: 0512CC5201 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2015 09:15:18.8558 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB344 Cc: Zhao Qiang Subject: [U-Boot] [PATCH v2] T2080QDS/PCIe: Soft Reset PCIe for down-training issue X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" T2080QDS PEX1/Slot#1 will down-train from x4 to x2, Soft reset PCIe can fix this issue, this is a workaround. Signed-off-by: Zhao Qiang --- changes for v2 - modify the commit message drivers/pci/fsl_pci_init.c | 17 +++++++++++++++++ include/configs/T208xQDS.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b075..327fa7d 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) #endif } +#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET + int i; + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { + pci_hose_read_config_word(hose, dev, PCI_LTSSM, + <ssm); + udelay(1000); + } + +#endif + #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..851b4f9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCIE_T2080QDS_RESET #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */