From patchwork Tue Feb 24 22:52:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 443258 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6A99E140083 for ; Wed, 25 Feb 2015 09:58:44 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E4FCD4B61F; Tue, 24 Feb 2015 23:58:28 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IAzq3NOc8uah; Tue, 24 Feb 2015 23:58:28 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6EB274A04E; Tue, 24 Feb 2015 23:58:06 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C20AF4A02F for ; Tue, 24 Feb 2015 23:53:35 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rx6hmfcKyQuT for ; Tue, 24 Feb 2015 23:53:35 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 2D7EB4A029 for ; Tue, 24 Feb 2015 23:53:34 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t1OMqVp1016986; Tue, 24 Feb 2015 16:52:31 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1OMqTdt001107; Tue, 24 Feb 2015 16:52:29 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Tue, 24 Feb 2015 16:52:29 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1OMqTeg007554; Tue, 24 Feb 2015 16:52:29 -0600 From: Nishanth Menon To: Lokesh Vutla , "Franklin Cooper Jr." , Felipe Balbi , Jeroen Hofstee , Paul Kocialkowski , Dirk Behme , Peng Fan , Georges Savoundararadj , Nitin Garg , Guillaume GARDET , Holger Freyther , Jeremiah Mahler , Thierry Reding , Josh Wu , Marek Vasut , Heiko Schocher , Masahiro Yamada , York Sun , Simon Glass , Thomas Weber , Stefan Roese , Nishanth Menon , Grazvydas Ignotas , Michael Jones , Peter Barada , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Ilya Yanok , Luca Ceresoli , Igor Grinberg , Nagendra T S , Albert Aribaud Date: Tue, 24 Feb 2015 16:52:10 -0600 Message-ID: <1424818334-29398-6-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1424818334-29398-1-git-send-email-nm@ti.com> References: <1424818334-29398-1-git-send-email-nm@ti.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 24 Feb 2015 23:57:51 +0100 Cc: Akshay Saraswat , u-boot@lists.denx.de, angelabaker@ti.com, vchengalvala@ti.com, prao@ti.com, Kimoon Kim Subject: [U-Boot] [PATCH V2 5/9] ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Praveen Rao This patch adds workaround for ARM errata 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An implementation for OMAP5 and DRA7 is introduced here as well. Obviously, implementations for other SoC families such as Exynos etc will be widely different. Signed-off-by: Praveen Rao Signed-off-by: Angela Stegmaier Signed-off-by: Nishanth Menon --- README | 1 + arch/arm/cpu/armv7/omap5/Makefile | 1 + arch/arm/cpu/armv7/omap5/lowlevel_init.S | 46 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + 4 files changed, 49 insertions(+) create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S diff --git a/README b/README index 2e53e0c5757d..d76cdc68d406 100644 --- a/README +++ b/README @@ -625,6 +625,7 @@ The following options need to be configured: with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an SoC specific implementation of the erratum workaround to function. + CONFIG_ARM_ERRATA_798870 - Driver Model Driver model is a new framework for devices in U-Boot diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index 64c68791f18e..b645dd4f58b7 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -11,3 +11,4 @@ obj-y += sdram.o obj-y += prcm-regs.o obj-y += hw_data.o obj-y += abb.o +obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/armv7/omap5/lowlevel_init.S b/arch/arm/cpu/armv7/omap5/lowlevel_init.S new file mode 100644 index 000000000000..974e3a59fb08 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/lowlevel_init.S @@ -0,0 +1,46 @@ +/* + * Board specific misc setup + * + * (C) Copyright 2015 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define OMAP5_SERVICE_L2ACTLR_SET 0x104 + +#ifdef CONFIG_ARM_ARCH_CP15_ERRATA + .globl arch_cp15_errata_workaround +/* + * R0 has MIDR + * R1 has CPU Variant (bits 20-23) + * R2 has CPU Revision (bits 0-3) + * R3 is compbined CPU variant << 4 + CPU revision + */ +ENTRY(arch_cp15_errata_workaround) + push {r4-r11, lr} @ save registers - ROM code may pollute + +#ifdef CONFIG_ARM_ERRATA_798870 + /* We are r2p2, but anyways for completeness.. */ + cmp r3, #0x30 @ Applies to lower than R3p0 + bge skip_errata_798870 @ skip if not affected rev + cmp r3, #0x20 @ Applies to including and above R2p0 + blt skip_errata_798870 @ skip if not affected rev + + mrc p15, 1, r1, c15, c0, 0 @ read l2 aux ctrl reg + orr r1, r1, #1 << 7 @ set bit #7 + ldr r0, =OMAP5_SERVICE_L2ACTLR_SET @ Set L2 Cache Auxiliary control register - value in R0 + b omap_smc1 + +skip_errata_798870: +#endif + pop {r4-r11, pc} +ENDPROC(arch_cp15_errata_workaround) + +#endif diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 103830319a41..0a7a52d138df 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -56,6 +56,7 @@ void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); void setup_warmreset_time(void); +void omap_smc1(u32 service, u32 val); static inline u32 div_round_up(u32 num, u32 den) {