From patchwork Tue Feb 24 22:52:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 443255 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 248F4140083 for ; Wed, 25 Feb 2015 09:58:08 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2851A4B5CB; Tue, 24 Feb 2015 23:58:02 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kfmun0gcO2E9; Tue, 24 Feb 2015 23:58:02 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D2EB84A03B; Tue, 24 Feb 2015 23:57:56 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9D9254A020 for ; Tue, 24 Feb 2015 23:53:26 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id n_izHNfG5_Tz for ; Tue, 24 Feb 2015 23:53:26 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 228AA4A01C for ; Tue, 24 Feb 2015 23:53:23 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t1OMqVJN008716; Tue, 24 Feb 2015 16:52:31 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1OMqTTm001101; Tue, 24 Feb 2015 16:52:30 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Tue, 24 Feb 2015 16:52:28 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1OMqTMG016293; Tue, 24 Feb 2015 16:52:29 -0600 From: Nishanth Menon To: Lokesh Vutla , "Franklin Cooper Jr." , Felipe Balbi , Jeroen Hofstee , Paul Kocialkowski , Dirk Behme , Peng Fan , Georges Savoundararadj , Nitin Garg , Guillaume GARDET , Holger Freyther , Jeremiah Mahler , Thierry Reding , Josh Wu , Marek Vasut , Heiko Schocher , Masahiro Yamada , York Sun , Simon Glass , Thomas Weber , Stefan Roese , Nishanth Menon , Grazvydas Ignotas , Michael Jones , Peter Barada , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Ilya Yanok , Luca Ceresoli , Igor Grinberg , Nagendra T S , Albert Aribaud Date: Tue, 24 Feb 2015 16:52:09 -0600 Message-ID: <1424818334-29398-5-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1424818334-29398-1-git-send-email-nm@ti.com> References: <1424818334-29398-1-git-send-email-nm@ti.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 24 Feb 2015 23:57:51 +0100 Cc: Akshay Saraswat , u-boot@lists.denx.de, angelabaker@ti.com, vchengalvala@ti.com, prao@ti.com, Kimoon Kim Subject: [U-Boot] [PATCH V2 4/9] ARM: Provide a mechanism to invoke SoC specific errata WA for CP15 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an ARCH specific macro is introduced to implement SoC specific errata workaround implementations. Signed-off-by: Nishanth Menon --- README | 5 +++++ arch/arm/cpu/armv7/start.S | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/README b/README index a28ff133ee05..2e53e0c5757d 100644 --- a/README +++ b/README @@ -621,6 +621,11 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply! + NOTE: The following are machine specific errata that are enabled + with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an + SoC specific implementation of the erratum workaround to + function. + - Driver Model Driver model is a new framework for devices in U-Boot introduced in early 2014. U-Boot is being progressively diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 70048c10aee6..3b814d8f42d3 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -163,6 +163,20 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ARCH_CP15_ERRATA + mrc p15, 0, r0, c0, c0, 0 @ r0 has Read Main ID Register (MIDR) + mov r1, r0, lsr #20 @ get variant field + and r1, r1, #0xf @ r1 has CPU variant + and r2, r0, #0xf @ r2 has CPU revision + mov r3, r1, lsl #4 @ shift variant field for combined value + orr r3, r2, r3 @ r3 has combined CPU variant + revision + /* C Prototype: + * void arch_cp15_errata_workaround(u32 midr, u32 variant, + * u32 rev, u32 comb); + */ + b arch_cp15_errata_workaround @ Do Machine specific errata WAs +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)