From patchwork Tue Feb 17 22:29:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 440741 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3580F1401DD for ; Wed, 18 Feb 2015 09:32:28 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1E4AC4B664; Tue, 17 Feb 2015 23:31:46 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1PxemVOgRAzG; Tue, 17 Feb 2015 23:31:46 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E08964B782; Tue, 17 Feb 2015 23:31:13 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6D0B04B654 for ; Tue, 17 Feb 2015 23:30:15 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id o20NSl0Af_uN for ; Tue, 17 Feb 2015 23:30:15 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f202.google.com (mail-ob0-f202.google.com [209.85.214.202]) by theia.denx.de (Postfix) with ESMTPS id 3B1484B683 for ; Tue, 17 Feb 2015 23:30:12 +0100 (CET) Received: by mail-ob0-f202.google.com with SMTP id nt9so13511097obb.1 for ; Tue, 17 Feb 2015 14:30:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qSo4aoLUoNJKNKruvIs+1rNlU/BN30MCZ8sJwIVYOUs=; b=CHI9l2yRsZoi+ARKiwNhtQ7aujzLZuKDRTWuzykBaq0I9gQkXGLCffRjxXpToEO6W7 11SioAtlOQ7tapRtT3eybEjm7tX8ORf7B+jNhrx12b0jFWf/UaC/a74JeROP/3uD4sYm U2UPBPIOYEalKK7Uuq/FxDwBXzTH3+qXuKnfs9xPvngo3hatgaeAaQtHz+CVCioQZY8/ l+DeB8OXWtCqaHSR0dhVqirO76fE8nGt8qwdscx56vbc9cqee48luzzcrhVeUhMbrxeQ +adrXS8TkWZB8jAZSXA0rgd5HUt6/ik6RRWzqUs9IFMncqyCJBK8V9K+0njC008iUA5l PJ2g== X-Gm-Message-State: ALoCoQkDaD8IYFO5sfjZuo9c94qnpjoTnolsExk39eQnSIlwwy3ohLHSUPjXbWccy5wNTl1M6+Ax X-Received: by 10.182.248.227 with SMTP id yp3mr17538355obc.22.1424212210958; Tue, 17 Feb 2015 14:30:10 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id kt5si4269523qcb.3.2015.02.17.14.30.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Feb 2015 14:30:10 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id GnzWA24f.2; Tue, 17 Feb 2015 14:30:10 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 5DF65220784; Tue, 17 Feb 2015 15:30:10 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Tue, 17 Feb 2015 15:29:51 -0700 Message-Id: <1424212195-7501-18-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1424212195-7501-1-git-send-email-sjg@chromium.org> References: <1424212195-7501-1-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH 17/20] tegra: nyan-big: Add additional clock and kernel init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We need to turn on all audio-related clocks for the kernel to boot. Otherwise it will hang when trying to enable audio. Also for Linux set up the ODMDATA and graphics driver video protection. Signed-off-by: Simon Glass --- board/nvidia/nyan-big/nyan-big.c | 76 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ae8874b..987ec7c 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -8,7 +8,12 @@ #include #include #include +#include #include +#include +#include +#include +#include #include #include #include "pinmux-config-nyan-big.h" @@ -57,3 +62,74 @@ int tegra_lcd_pmic_init(int board_id) return 0; } + +/* Setup required information for Linux kernel */ +static void setup_kernel_info(void) +{ + struct pmc_ctlr *pmc = (void *)NV_PA_PMC_BASE; + struct mc_ctlr *mc = (void *)NV_PA_MC_BASE; + + /* + * pmc.odmdata: [18:19]: console type, [15:17]: UART id + * TODO: Derive this from the current settings + */ + writel(0x80080000, &pmc->pmc_scratch20); + + /* The kernel graphics driver needs this region locked down */ + writel(0, &mc->mc_video_protect_bom); + writel(0, &mc->mc_video_protect_size_mb); + writel(1, &mc->mc_video_protect_reg_ctrl); +} + +/* + * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF, + * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks. + * Otherwise reading AHUB devices will hang when the kernel boots. + */ +static void enable_required_clocks(void) +{ + static enum periph_id ids[] = { + PERIPH_ID_I2S0, + PERIPH_ID_I2S1, + PERIPH_ID_I2S2, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_AMX0, + PERIPH_ID_AMX1, + PERIPH_ID_ADX0, + PERIPH_ID_ADX1, + PERIPH_ID_SPDIF, + PERIPH_ID_AFC0, + PERIPH_ID_AFC1, + PERIPH_ID_AFC2, + PERIPH_ID_AFC3, + PERIPH_ID_AFC4, + PERIPH_ID_AFC5, + PERIPH_ID_EXTPERIPH1 + }; + int i; + + for (i = 0; i < ARRAY_SIZE(ids); i++) + clock_enable(ids[i]); + udelay(2); + for (i = 0; i < ARRAY_SIZE(ids); i++) + reset_set_enable(ids[i], 0); +} + +int nvidia_board_init(void) +{ + clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000); + clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000); + + /* For external MAX98090 audio codec */ + clock_external_output(1); + setup_kernel_info(); + enable_required_clocks(); + + return 0; +}