diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f12dac9..d49142e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -365,10 +365,6 @@ config TARGET_INTEGRATORCP_CM1136
 	bool "Support integratorcp_cm1136"
 	select CPU_ARM1136
 
-config TARGET_IMX31_PHYCORE
-	bool "Support imx31_phycore"
-	select CPU_ARM1136
-
 config TARGET_QONG
 	bool "Support qong"
 	select CPU_ARM1136
@@ -934,7 +930,6 @@ source "board/gumstix/pepper/Kconfig"
 source "board/h2200/Kconfig"
 source "board/hale/tt01/Kconfig"
 source "board/icpdas/lp8x4x/Kconfig"
-source "board/imx31_phycore/Kconfig"
 source "board/isee/igep0033/Kconfig"
 source "board/jornada/Kconfig"
 source "board/karo/tx25/Kconfig"
diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig
deleted file mode 100644
index d3d2025..0000000
--- a/board/imx31_phycore/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_IMX31_PHYCORE
-
-config SYS_BOARD
-	default "imx31_phycore"
-
-config SYS_SOC
-	default "mx31"
-
-config SYS_CONFIG_NAME
-	default "imx31_phycore"
-
-endif
diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS
deleted file mode 100644
index 41f6cae..0000000
--- a/board/imx31_phycore/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-IMX31_PHYCORE BOARD
-#M:	-
-S:	Maintained
-F:	board/imx31_phycore/
-F:	include/configs/imx31_phycore.h
-F:	configs/imx31_phycore_defconfig
-
-IMX31_PHYCORE_EET BOARD
-#M:	(resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-S:	Orphan (since 2013-09)
-F:	configs/imx31_phycore_eet_defconfig
diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile
deleted file mode 100644
index e781c13..0000000
--- a/board/imx31_phycore/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= imx31_phycore.o
-obj-y	+= lowlevel_init.o
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
deleted file mode 100644
index 3f45e4e..0000000
--- a/board/imx31_phycore/imx31_phycore.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <common.h>
-#include <s6e63d6.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
-				PHYS_SDRAM_1_SIZE);
-	return 0;
-}
-
-int board_init(void)
-{
-
-	gd->bd->bi_arch_number = MACH_TYPE_PCM037;	/* board id for linux */
-	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* CS0: Nor Flash */
-	static const struct mxc_weimcs cs0 = {
-		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
-		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 15, 0,  0,  3),
-		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
-		CSCR_L(1,  0,   0,   0,  0,  1,  5,  0,  0,  0,   1,   1),
-		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
-		CSCR_A(0,   0,  7,  2,  0,  0,  2,  1,  0,  0,  0,  0,   0,  0)
-	};
-
-	/* CS1: Network Controller */
-	static const struct mxc_weimcs cs1 = {
-		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
-		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 31, 0,  0,  6),
-		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
-		CSCR_L(4,  4,   4,  10,  4,  0,  5,  4,  0,  0,   0,   1),
-		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
-		CSCR_A(4,   4,  4,  4,  0,  1,  4,  3,  0,  0,  0,  0,   1,  0)
-	};
-
-	/* CS4: SRAM */
-	static const struct mxc_weimcs cs4 = {
-		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
-		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
-		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
-		CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
-		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
-		CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
-	};
-
-	mxc_setup_weimcs(0, &cs0);
-	mxc_setup_weimcs(1, &cs1);
-	mxc_setup_weimcs(4, &cs4);
-
-	/* setup pins for UART1 */
-	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
-	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
-	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
-	/* setup pins for I2C2 (for EEPROM, RTC) */
-	mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
-	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
-
-	return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_S6E63D6
-	struct s6e63d6 data = {
-		/*
-		 * See comment in mxc_spi.c::decode_cs() for .cs field format.
-		 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
-		 * 2 of the SPI controller #1, since it is unused.
-		 */
-		.cs = 2 | (57 << 8),
-		.bus = 0,
-		.id = 0,
-	};
-	int ret;
-
-	/* SPI1 */
-	mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
-	mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
-	mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
-	mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
-	mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
-	mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
-	mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
-
-	/* start SPI1 clock */
-	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
-
-	/* GPIO 57 */
-	/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
-	mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
-
-	/* SPI1 CS2 is free */
-	ret = s6e63d6_init(&data);
-	if (ret)
-		return ret;
-
-	/*
-	 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
-	 * OLED display connected to a S6E63D6 SPI display controller in the
-	 * 18 bit RGB mode
-	 */
-	s6e63d6_index(&data, 2);
-	s6e63d6_param(&data, 0x0182);
-	s6e63d6_index(&data, 3);
-	s6e63d6_param(&data, 0x8130);
-	s6e63d6_index(&data, 0x10);
-	s6e63d6_param(&data, 0x0000);
-	s6e63d6_index(&data, 5);
-	s6e63d6_param(&data, 0x0001);
-	s6e63d6_index(&data, 0x22);
-#endif
-	return 0;
-}
-#endif
-
-int checkboard (void)
-{
-	printf("Board: Phytec phyCore i.MX31\n");
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-	return rc;
-}
diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
deleted file mode 100644
index 6ea3878..0000000
--- a/board/imx31_phycore/lowlevel_init.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
-	ldr r2, =\reg
-	ldr r3, =\val
-	str r3, [r2]
-.endm
-
-.macro REG8 reg, val
-	ldr r2, =\reg
-	ldr r3, =\val
-	strb r3, [r2]
-.endm
-
-.macro DELAY loops
-	ldr r2, =\loops
-1:
-	subs	r2, r2, #1
-	nop
-	bcs 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
-	REG	IPU_CONF, IPU_CONF_DI_EN
-	REG	CCM_CCMR, 0x074B0BF5
-
-	DELAY 0x40000
-
-	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
-	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
-	REG	CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
-
-	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
-
-	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
-
-	REG	0x43FAC26C, 0 /* SDCLK */
-	REG	0x43FAC270, 0 /* CAS */
-	REG	0x43FAC274, 0 /* RAS */
-	REG	0x43FAC27C, 0x1000 /* CS2 (CSD0) */
-	REG	0x43FAC284, 0 /* DQM3 */
-	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
-	REG	0x43FAC28C, 0
-	REG	0x43FAC290, 0
-	REG	0x43FAC294, 0
-	REG	0x43FAC298, 0
-	REG	0x43FAC29C, 0
-	REG	0x43FAC2A0, 0
-	REG	0x43FAC2A4, 0
-	REG	0x43FAC2A8, 0
-	REG	0x43FAC2AC, 0
-	REG	0x43FAC2B0, 0
-	REG	0x43FAC2B4, 0
-	REG	0x43FAC2B8, 0
-	REG	0x43FAC2BC, 0
-	REG	0x43FAC2C0, 0
-	REG	0x43FAC2C4, 0
-	REG	0x43FAC2C8, 0
-	REG	0x43FAC2CC, 0
-	REG	0x43FAC2D0, 0
-	REG	0x43FAC2D4, 0
-	REG	0x43FAC2D8, 0
-	REG	0x43FAC2DC, 0
-	REG	0xB8001010, 0x00000004
-	REG	0xB8001004, 0x006ac73a
-	REG	0xB8001000, 0x92100000
-	REG	0x80000f00, 0x12344321
-	REG	0xB8001000, 0xa2100000
-	REG	0x80000000, 0x12344321
-	REG	0x80000000, 0x12344321
-	REG	0xB8001000, 0xb2100000
-	REG8	0x80000033, 0xda
-	REG8	0x81000000, 0xff
-	REG	0xB8001000, 0x82226080
-	REG	0x80000000, 0xDEADBEEF
-	REG	0xB8001010, 0x0000000c
-
-	mov	pc, lr
diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig
deleted file mode 100644
index 563de57..0000000
--- a/configs/imx31_phycore_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_IMX31_PHYCORE=y
diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig
deleted file mode 100644
index 9531952..0000000
--- a/configs/imx31_phycore_eet_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET"
-CONFIG_ARM=y
-CONFIG_TARGET_IMX31_PHYCORE=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index c6f3d14..cd51249 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+imx31_phycore    arm         arm1136        -           -           Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 mx31ads          arm         arm1136        -           -           Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 icecube_5200     powerpc     mpc5xxx        37b608a5    2015-01-23  Wolfgang Denk <wd@denx.de>
 Lite5200         powerpc     mpc5xxx        37b608a5    2015-01-23
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
deleted file mode 100644
index 4195fa3..0000000
--- a/include/configs/imx31_phycore.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Kshitij Gupta <kshitij@ti.com>
- *
- * Configuration settings for the phyCORE-i.MX31 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-#define CONFIG_MX31			/* This is a mx31 */
-#define CONFIG_MX31_CLK32	32000
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE		UART1_BASE
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-
-#define CONFIG_BOOTDELAY	3
-
-#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
-					"1536k(kernel),-(root)"
-
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.23.168
-#define CONFIG_SERVERIP		192.168.23.2
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
-	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
-		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
-	"bootargs_flash=setenv bootargs $(bootargs) "			\
-		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
-	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
-	"bootcmd=run bootcmd_net\0"					\
-	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
-		"tftpboot 0x80000000 $(uimage);bootm\0"			\
-	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
-		"bootm 0x80000000\0"					\
-	"unlock=yes\0"							\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
-	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
-		"protect off 0xa0000000 +0x20000;"			\
-		"erase 0xa0000000 +0x20000;"				\
-		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
-	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
-		"erase 0xa0040000 +0x180000;"				\
-		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
-	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
-		"erase 0xa01c0000 0xa1ffffff;"				\
-		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
-	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
-		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
-		"sync:1241513985,vmode:0\0"
-
-
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE	0xa8000000
-#define CONFIG_SMC911X_32_BIT
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"uboot> "
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x10000
-
-#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
-
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x80000000
-#define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SYS_TEXT_BASE		0xA0000000
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE		0xa0000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
-#define CONFIG_ENV_SIZE				4096
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */
-
-/*
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
-
-/*
- * Timeout for Flash Erase and Flash Write
- * timeout values are in ticks
- */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)
-
-/*
- * JFFS2 partitions
- */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV	"nor0"
-
-/* EET platform additions */
-#ifdef CONFIG_IMX31_PHYCORE_EET
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_HARD_SPI
-#define CONFIG_MXC_SPI
-#define CONFIG_CMD_SPI
-
-#define CONFIG_S6E63D6
-
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_MX3
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_CMD_BMP
-#define CONFIG_BMP_16BPP
-#endif
-
-#endif /* __CONFIG_H */
