From patchwork Sat Jan 31 22:27:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Siamashka X-Patchwork-Id: 435192 X-Patchwork-Delegate: hdegoede@redhat.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3ACCC1402F7 for ; Sun, 1 Feb 2015 09:27:37 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4526E4A04F; Sat, 31 Jan 2015 23:27:30 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GZ_cf5EOHEpl; Sat, 31 Jan 2015 23:27:30 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 613CE4B576; Sat, 31 Jan 2015 23:27:23 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B7BA64A032 for ; Sat, 31 Jan 2015 23:27:15 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RnhxXzpuurY8 for ; Sat, 31 Jan 2015 23:27:15 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-la0-f50.google.com (mail-la0-f50.google.com [209.85.215.50]) by theia.denx.de (Postfix) with ESMTPS id 7F1324A033 for ; Sat, 31 Jan 2015 23:27:13 +0100 (CET) Received: by mail-la0-f50.google.com with SMTP id hs14so30805751lab.9 for ; Sat, 31 Jan 2015 14:27:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yNKbFZ37mx8PTNqXGXSBp9UCfwXMGBmAuX1D8jN0zMI=; b=prqREhWp27iMdpR9JKUrawtw0NK6mqFBJOl8oJ6A3ZC+DyUND/NpUGb0n/V6bqNkq2 1kGa7FelW7FjCLLf8Z29NBwylbwifkdqBsrXKZ9/jQLppXsp3i6X8aSxpxKUNEB+L4kM xYwkX5FS/M7Hlfu7Q72FJDqmAJIu2i9WcQ79t0JJj1stxsn8RPAr4t+kmt2Yy+lxomqC V2avH0Qag+Sks5n842pdjIgO0AQaNU34Tlgswa0i+dH6Bu/WyCOXJUFNs7Fmb4ZvLXAm o7FIY+9dPebzsTQoiprHwYbPM5dgLIC+xMGn8TBmNrnK1ZpAvek3vxvdI2zfqtKw5/lC nZUQ== X-Received: by 10.152.29.6 with SMTP id f6mr1195614lah.82.1422743233462; Sat, 31 Jan 2015 14:27:13 -0800 (PST) Received: from localhost.localdomain (85-76-74-251-nat.elisa-mobile.fi. [85.76.74.251]) by mx.google.com with ESMTPSA id ld6sm1422414lbc.22.2015.01.31.14.27.11 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 31 Jan 2015 14:27:12 -0800 (PST) From: Siarhei Siamashka To: u-boot@lists.denx.de Date: Sun, 1 Feb 2015 00:27:06 +0200 Message-Id: <1422743227-24097-3-git-send-email-siarhei.siamashka@gmail.com> X-Mailer: git-send-email 2.0.5 In-Reply-To: <1422743227-24097-1-git-send-email-siarhei.siamashka@gmail.com> References: <1422743227-24097-1-git-send-email-siarhei.siamashka@gmail.com> Cc: Ian Campbell Subject: [U-Boot] [PATCH 2/3] sunxi: dram: Support more sun[457]i dram parameters in Kconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch allows to configure all the important DRAM parameters in Kconfig. Signed-off-by: Siarhei Siamashka --- board/sunxi/Kconfig | 43 +++++++++++++++++++++++++++++++++++++++++++ board/sunxi/dram_sun4i_auto.c | 6 ++++-- board/sunxi/dram_sun5i_auto.c | 5 ++++- 3 files changed, 51 insertions(+), 3 deletions(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index da4e8ba..4a21589 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -41,6 +41,15 @@ config DRAM_CLK Set the dram clock speed, valid range 240 - 480, must be a multiple of 24. +if MACH_SUN5I || MACH_SUN7I +config DRAM_MBUS_CLK + int "sunxi mbus clock speed" + default 300 + ---help--- + Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. + +endif + config DRAM_ZQ int "sunxi dram zq value" default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I @@ -56,6 +65,40 @@ config DRAM_EMR1 ---help--- Set the dram controller emr1 value. +config DRAM_ODT_EN + int "sunxi dram odt_en value" + default 0 + ---help--- + Set the dram controller odt_en parameter. This can be used to + enable/disable the ODT feature. + +config DRAM_TPR3 + hex "sunxi dram tpr3 value" + default 0 + ---help--- + Set the dram controller tpr3 parameter. This parameter configures + the delay on the command lane and also phase shifts, which are + applied for sampling incoming read data. The default value 0 + means that no phase/delay adjustments are necessary. Properly + configuring this parameter increases reliability at high DRAM + clock speeds. + +config DRAM_DQS_GATING_DELAY + hex "sunxi dram dqs_gating_delay value" + default 0 + ---help--- + Set the dram controller dqs_gating_delay parmeter. Each byte + encodes the DQS gating delay for each byte lane. The delay + granularity is 1/4 cycle. For example, the value 0x05060606 + means that the delay is 5 quarter-cycles for one lane (1.25 + cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. + The default value 0 means autodetection. The results of hardware + autodetection are not very reliable and depend on the chip + temperature (sometimes producing different results on cold start + and warm reboot). But the accuracy of hardware autodetection + is usually good enough, unless running at really high DRAM + clocks speeds (up to 600MHz). If unsure, keep as 0. + choice prompt "sunxi dram timings" default DRAM_TIMINGS_VENDOR_MAGIC diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c index ed54150..09e0c9a 100644 --- a/board/sunxi/dram_sun4i_auto.c +++ b/board/sunxi/dram_sun4i_auto.c @@ -9,7 +9,7 @@ static struct dram_para dram_para = { .io_width = 0, .bus_width = 0, .zq = CONFIG_DRAM_ZQ, - .odt_en = 0, + .odt_en = CONFIG_DRAM_ODT_EN, .size = 0, #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC .cas = 6, @@ -19,12 +19,14 @@ static struct dram_para dram_para = { .emr2 = 0, #else # include "dram_timings_sun4i.h" + .active_windowing = 1, #endif - .tpr3 = 0, + .tpr3 = CONFIG_DRAM_TPR3, .tpr4 = 0, .tpr5 = 0, .emr1 = CONFIG_DRAM_EMR1, .emr3 = 0, + .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, }; unsigned long sunxi_dram_init(void) diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index bd9fd4b..e52d54c 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -5,13 +5,14 @@ static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, + .mbus_clock = CONFIG_DRAM_MBUS_CLK, .type = 3, .rank_num = 1, .density = 0, .io_width = 0, .bus_width = 0, .zq = CONFIG_DRAM_ZQ, - .odt_en = 0, + .odt_en = CONFIG_DRAM_ODT_EN, .size = 0, #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC .cas = 9, @@ -21,12 +22,14 @@ static struct dram_para dram_para = { .emr2 = 0x10, #else # include "dram_timings_sun4i.h" + .active_windowing = 1, #endif .tpr3 = 0, .tpr4 = 0, .tpr5 = 0, .emr1 = CONFIG_DRAM_EMR1, .emr3 = 0, + .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, }; unsigned long sunxi_dram_init(void)