From patchwork Wed Jan 28 15:19:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 433894 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0B0AB140129 for ; Thu, 29 Jan 2015 02:20:39 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AAD9C4B833; Wed, 28 Jan 2015 16:20:33 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hH2aLtWrcKys; Wed, 28 Jan 2015 16:20:33 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 314C24B823; Wed, 28 Jan 2015 16:20:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 522D34B80D for ; Wed, 28 Jan 2015 16:20:25 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FQhiiv4YIPBo for ; Wed, 28 Jan 2015 16:20:25 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f41.google.com (mail-pa0-f41.google.com [209.85.220.41]) by theia.denx.de (Postfix) with ESMTPS id 528C04B802 for ; Wed, 28 Jan 2015 16:20:24 +0100 (CET) Received: by mail-pa0-f41.google.com with SMTP id kq14so26399893pab.0 for ; Wed, 28 Jan 2015 07:20:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=5rcZHJMZ25fyrR29BkWd/LmiOBkS+TchyNE6P6w7Pbk=; b=Aa7HSBSpQh2cVNvSpuXk3aV4TnNqH78CU0hfDoKvIyaZoIfxL5bs1o9IIShQMcGTgv pNUI3OCx3jtQUKy+wr7IKcDIYmhhID592fPWHz9GWNtsc2SnO4V23irfNtPlfYjJH8+K MmHyjL1ppmaoLnljpAmH9+YXgIfaD2HmyIyNv1n+GM2wZFR1MUlD7+u2yGOuiDCx6Rec 33XIR36hRn8FfcYb3260Jyw8hK/9UasdYTH11oMgqkB6vqKjr1ODXXIpkju+GtSgRLLy L8pWiw89bRQMR8DGIB8zYN7w7Mi0HLjqLFLF/PxJodZYAtQmikoPgzXup0iITsakowy1 oq8w== X-Received: by 10.66.222.227 with SMTP id qp3mr6691992pac.47.1422458422958; Wed, 28 Jan 2015 07:20:22 -0800 (PST) Received: from localhost ([106.120.101.38]) by mx.google.com with ESMTPSA id j8sm5009936pdo.79.2015.01.28.07.20.20 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 28 Jan 2015 07:20:22 -0800 (PST) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Wed, 28 Jan 2015 23:19:58 +0800 Message-Id: <1422458402-9187-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1422458402-9187-1-git-send-email-bmeng.cn@gmail.com> References: <1422458402-9187-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [RFC PATCH 2/6] x86: quark: Add routines to access message bus registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng --- arch/x86/cpu/quark/msg_port.c | 76 ++++++++++++++++++++++++ arch/x86/include/asm/arch-quark/msg_port.h | 93 ++++++++++++++++++++++++++++++ 2 files changed, 169 insertions(+) create mode 100644 arch/x86/cpu/quark/msg_port.c create mode 100644 arch/x86/include/asm/arch-quark/msg_port.h diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c new file mode 100644 index 0000000..a04462f --- /dev/null +++ b/arch/x86/cpu/quark/msg_port.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +u32 msg_port_read(u8 port, u32 reg) +{ + u32 value; + + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, + MCR_FILL(MSG_OP_READ, port, reg)); + pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + + return value; +} + +void msg_port_write(u8 port, u32 reg, u32 value) +{ + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, + MCR_FILL(MSG_OP_WRITE, port, reg)); +} + +u32 msg_port_alt_read(u8 port, u32 reg) +{ + u32 value; + + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, + MCR_FILL(MSG_OP_ALT_READ, port, reg)); + pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + + return value; +} + +void msg_port_alt_write(u8 port, u32 reg, u32 value) +{ + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, + MCR_FILL(MSG_OP_ALT_WRITE, port, reg)); +} + +u32 msg_port_io_read(u8 port, u32 reg) +{ + u32 value; + + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, + MCR_FILL(MSG_OP_IO_READ, port, reg)); + pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + + return value; +} + +void msg_port_io_write(u8 port, u32 reg, u32 value) +{ + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, + MCR_FILL(MSG_OP_IO_WRITE, port, reg)); +} diff --git a/arch/x86/include/asm/arch-quark/msg_port.h b/arch/x86/include/asm/arch-quark/msg_port.h new file mode 100644 index 0000000..8f40adb --- /dev/null +++ b/arch/x86/include/asm/arch-quark/msg_port.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _QUARK_MSG_PORT_H_ +#define _QUARK_MSG_PORT_H_ + +/* + * In the Quark SoC, some chipset commands are accomplished by utilizing + * the internal message network within the host bridge (D0:F0). Accesses + * to this network are accomplished by populating the message control + * register (MCR), Message Control Register eXtension (MCRX) and the + * message data register (MDR). + */ +#define MSG_CTRL_REG 0xD0 /* Message Control Register */ +#define MSG_CTRL_EXT_REG 0xD4 /* Message Control Register EXT */ +#define MSG_DATA_REG 0xD8 /* Message Data Register */ + +/* Normal Read/Write OpCodes */ +#define MSG_OP_READ 0x10 +#define MSG_OP_WRITE 0x11 + +/* Alternative Read/Write OpCodes */ +#define MSG_OP_ALT_READ 0x06 +#define MSG_OP_ALT_WRITE 0x07 + +/* IO Read/Write OpCodes */ +#define MSG_OP_IO_READ 0x02 +#define MSG_OP_IO_WRITE 0x03 + +#define MCR_FILL(op, port, reg) \ + (((op) << 24) | ((port) << 16) | (((reg) << 8) & 0xff00) | 0xf0) + +/** + * msg_port_read - read a message port register using normal opcode + * + * @port: port number on the message bus + * @reg: register number within a port + * + * @return: message port register value + */ +u32 msg_port_read(u8 port, u32 reg); + +/** + * msg_port_write - write a message port register using normal opcode + * + * @port: port number on the message bus + * @reg: register number within a port + * @value: register value to write + */ +void msg_port_write(u8 port, u32 reg, u32 value); + +/** + * msg_port_alt_read - read a message port register using alternative opcode + * + * @port: port number on the message bus + * @reg: register number within a port + * + * @return: message port register value + */ +u32 msg_port_alt_read(u8 port, u32 reg); + +/** + * msg_port_alt_write - write a message port register using alternative opcode + * + * @port: port number on the message bus + * @reg: register number within a port + * @value: register value to write + */ +void msg_port_alt_write(u8 port, u32 reg, u32 value); + +/** + * msg_port_io_read - read a message port register using I/O opcode + * + * @port: port number on the message bus + * @reg: register number within a port + * + * @return: message port register value + */ +u32 msg_port_io_read(u8 port, u32 reg); + +/** + * msg_port_io_write - write a message port register using I/O opcode + * + * @port: port number on the message bus + * @reg: register number within a port + * @value: register value to write + */ +void msg_port_io_write(u8 port, u32 reg, u32 value); + +#endif /* _QUARK_MSG_PORT_H_ */