From patchwork Thu Jan 22 03:29:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 431664 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B7FAA140276 for ; Thu, 22 Jan 2015 14:30:17 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 66B8D4B65B; Thu, 22 Jan 2015 04:30:11 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xiW6ViwSuhGI; Thu, 22 Jan 2015 04:30:11 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DE88D4B62C; Thu, 22 Jan 2015 04:30:09 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 605CD4B610 for ; Thu, 22 Jan 2015 04:30:03 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rWlkBb34j7mH for ; Thu, 22 Jan 2015 04:30:03 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f172.google.com (mail-pd0-f172.google.com [209.85.192.172]) by theia.denx.de (Postfix) with ESMTPS id 637244B622 for ; Thu, 22 Jan 2015 04:29:58 +0100 (CET) Received: by mail-pd0-f172.google.com with SMTP id v10so32360875pde.3 for ; Wed, 21 Jan 2015 19:29:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=WogPgnrlpgZVJsCO6PKaEio3IBPeK/TJMbbLylTLg30=; b=maQW6KVuU/6GNicAkUFsbQDomyJgY1M6yMDZ6G+GCBa/hy6hHHHzFVbgxHRDFxLdiT U2djU4evm9uOdJGVS5lpg54+BTpTsihuvroNMExxicJ1QF3S/D5C+yDndia1uTcG4gP/ wVRWBNhCGymXXR7m0eDcAD//W0kmh09dAtrZvOR+iTEho4h3hWDveIOdHNg2QFUq6M0z HKbDDjw5dICUTx2padOGqgJsqmG1MZut9PJFMkr3dKkh8K7dK1HQGNd4Nbwbh2APAyyS SLib9pdz2BT2aAM7r/xKJYdM4MAZPbKZupwmmh3f1xuK7R4d0rsHQ1ivHC/ieUG/8a29 ahPQ== X-Received: by 10.66.184.206 with SMTP id ew14mr66214068pac.3.1421897397180; Wed, 21 Jan 2015 19:29:57 -0800 (PST) Received: from localhost ([106.120.101.38]) by mx.google.com with ESMTPSA id ej7sm7102200pac.21.2015.01.21.19.29.55 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 21 Jan 2015 19:29:56 -0800 (PST) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Thu, 22 Jan 2015 11:29:41 +0800 Message-Id: <1421897381-27920-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1421897381-27920-1-git-send-email-bmeng.cn@gmail.com> References: <1421897381-27920-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v2 3/3] x86: Test mtrr support flag before accessing mtrr msr X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v2: - Return -ENOSYS in mtrr_commit() and mtrr_add_request() when MTRR MSR is not implemented in the processor - Add return value description of mtrr_commit() and mtrr_add_request() - Ignore -ENOSYS in init_cache_f_r() in arch/x86/lib/init_helpers.c arch/x86/cpu/mtrr.c | 12 ++++++++++++ arch/x86/include/asm/mtrr.h | 5 ++++- arch/x86/lib/init_helpers.c | 4 +++- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index ac8765f..5d36b3e 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -22,6 +22,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Prepare to adjust MTRRs */ void mtrr_open(struct mtrr_state *state) { + if (!gd->arch.has_mtrr) + return; + state->enable_cache = dcache_status(); if (state->enable_cache) @@ -33,6 +36,9 @@ void mtrr_open(struct mtrr_state *state) /* Clean up after adjusting MTRRs, and enable them */ void mtrr_close(struct mtrr_state *state) { + if (!gd->arch.has_mtrr) + return; + wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN); if (state->enable_cache) enable_caches(); @@ -45,6 +51,9 @@ int mtrr_commit(bool do_caches) uint64_t mask; int i; + if (!gd->arch.has_mtrr) + return -ENOSYS; + mtrr_open(&state); for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) { mask = ~(req->size - 1); @@ -66,6 +75,9 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size) struct mtrr_request *req; uint64_t mask; + if (!gd->arch.has_mtrr) + return -ENOSYS; + if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS) return -ENOSPC; req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++]; diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 3c11740..fda4eae 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -65,7 +65,6 @@ void mtrr_open(struct mtrr_state *state); * * @state: Structure from mtrr_open() */ -/* */ void mtrr_close(struct mtrr_state *state); /** @@ -76,6 +75,8 @@ void mtrr_close(struct mtrr_state *state); * @type: Requested type (MTRR_TYPE_) * @start: Start address * @size: Size + * + * @return: 0 on success, non-zero on failure */ int mtrr_add_request(int type, uint64_t start, uint64_t size); @@ -86,6 +87,8 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size); * It must be called with caches disabled. * * @do_caches: true if caches are currently on + * + * @return: 0 on success, non-zero on failure */ int mtrr_commit(bool do_caches); diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index fc211d9..5097ca2 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -71,7 +72,8 @@ int init_cache_f_r(void) int ret; ret = mtrr_commit(false); - if (ret) + /* If MTRR MSR is not implemented by the processor, just ignore it */ + if (ret && ret != -ENOSYS) return ret; #endif /* Initialise the CPU cache(s) */