From patchwork Mon Jan 19 16:26:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Gmeiner X-Patchwork-Id: 430603 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 39FC31401EB for ; Tue, 20 Jan 2015 03:27:55 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2B71E4B7EE; Mon, 19 Jan 2015 17:27:38 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id scGJ9630x07X; Mon, 19 Jan 2015 17:27:37 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0E9B94B7EF; Mon, 19 Jan 2015 17:27:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9F60F4B7BC for ; Mon, 19 Jan 2015 17:27:23 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id i2F4b-9vSXkh for ; Mon, 19 Jan 2015 17:27:23 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) by theia.denx.de (Postfix) with ESMTPS id DEE954B7DA for ; Mon, 19 Jan 2015 17:27:15 +0100 (CET) Received: by mail-wi0-f169.google.com with SMTP id bs8so17829707wib.0 for ; Mon, 19 Jan 2015 08:27:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+GKRheI4xymACBaS4wZ0hX0vtMYG/bRfUCokdyrTz40=; b=Ct2BCOY42m53m4IdKChENVCvuYBv4/vZZ7EbUnWYUorcoHZIlcG8UAZncRwDaEiWYk Z2NS37c1WnHHvjRW207Z+SHUmx7gjrse5ILRcIB9FDw70bQFk16bBhMF89bzXmC0A2ZT pPn88qS+W5PqUXdRCXSff+RO+khZvNUt6hiKcEj9ID8qcbaQKdiQcCDEgl8IfZTuUQ4B OY9bUAK/tWGLCcrTp0ilZ1fuj5eLk4iSciG76WK1BwFKdaqxeaVYTu3UrrAhEwFs77Gh 41Au+0rhTWzwKypTq5zkfiKxkA3hnrAxbzX00hw816Ij9mS9hHD6WN2FGX+pfMIxiTkg WtAg== X-Received: by 10.194.9.4 with SMTP id v4mr62611309wja.115.1421684835042; Mon, 19 Jan 2015 08:27:15 -0800 (PST) Received: from chgm-pc.bachmann.at.bachmann.at (089144207229.atnat0016.highway.bob.at. [89.144.207.229]) by mx.google.com with ESMTPSA id q10sm14515757wjr.41.2015.01.19.08.27.13 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Jan 2015 08:27:14 -0800 (PST) From: Christian Gmeiner To: u-boot@lists.denx.de Date: Mon, 19 Jan 2015 17:26:49 +0100 Message-Id: <1421684810-2684-7-git-send-email-christian.gmeiner@gmail.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1421684810-2684-1-git-send-email-christian.gmeiner@gmail.com> References: <1421684810-2684-1-git-send-email-christian.gmeiner@gmail.com> Subject: [U-Boot] [PATCH 6/7] ot1200: add basic SPL support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Currently we only support the Micron MT41K128M16JT-125 ddr3 chip. Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/Makefile | 4 + board/bachmann/ot1200/ot1200_spl.c | 162 +++++++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+) create mode 100644 board/bachmann/ot1200/ot1200_spl.c diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile index 1bd42e8..9e50bfe 100644 --- a/board/bachmann/ot1200/Makefile +++ b/board/bachmann/ot1200/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y := ot1200.o ot1200_spl.o +else obj-y := ot1200.o +endif diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c new file mode 100644 index 0000000..9c77fd3 --- /dev/null +++ b/board/bachmann/ot1200/ot1200_spl.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2015, Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */ + .dram_sdclk_0 = 0x00000028, + .dram_sdclk_1 = 0x00000028, + .dram_cas = 0x00000028, + .dram_ras = 0x00000028, + .dram_reset = 0x00000028, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 48 ohm */ + .dram_sdodt0 = 0x00000028, + .dram_sdodt1 = 0x00000028, + /* SDQS[0:7]: Differential input, 48 ohm */ + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_sdqs4 = 0x00000028, + .dram_sdqs5 = 0x00000028, + .dram_sdqs6 = 0x00000028, + .dram_sdqs7 = 0x00000028, + /* DQM[0:7]: Differential input, 48 ohm */ + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_dqm4 = 0x00000028, + .dram_dqm5 = 0x00000028, + .dram_dqm6 = 0x00000028, + .dram_dqm7 = 0x00000028, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* Disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 48 ohm */ + .grp_addds = 0x00000028, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */ + .grp_ctlds = 0x00000028, + /* DATA[00:63]: Differential input, 48 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, + .grp_b4ds = 0x00000028, + .grp_b5ds = 0x00000028, + .grp_b6ds = 0x00000028, + .grp_b7ds = 0x00000028, +}; + +static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = { + /* Width of data bus: 0=16, 1=32, 2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* Single chip select */ + .ncs = 1, + .cs1_mirror = 0, /* war 0 */ + .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ /* war 1 */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +/* MT41K128M16JT-125 */ +static struct mx6_ddr3_cfg micron_2gib_1600 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 1, +}; + +static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00260025, + .p0_mpwldectrl1 = 0x00270021, + .p1_mpwldectrl0 = 0x00180034, + .p1_mpwldectrl1 = 0x00180024, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x04380344, + .p0_mpdgctrl1 = 0x0330032C, + .p1_mpdgctrl0 = 0x0338033C, + .p1_mpdgctrl1 = 0x032C0300, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C2E3238, + .p1_mprddlctl = 0x3A2E303C, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36384036, + .p1_mpwrdlctl = 0x442E4438, +}; + +static void ot1200_spl_dram_init(void) +{ + mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs); + mx6_dram_cfg(&ot1200_ddr_sysinfo, µn_2gib_1600_mmdc_calib, + µn_2gib_1600); +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* configure MMDC for SDRAM width/size and per-model calibration */ + ot1200_spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +}