@@ -13,7 +13,9 @@ obj-y += board.o
obj-y += clock.o
obj-y += cpu_info.o
obj-y += pinmux.o
+ifndef CONFIG_MACH_SUN9I
obj-y += usbc.o
+endif
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
@@ -71,6 +71,10 @@ int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH12_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH13_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
@@ -11,6 +11,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <axp221.h>
+#include <errno.h>
#ifdef CONFIG_MACH_SUN6I
int sunxi_get_ss_bonding_id(void)
@@ -66,6 +67,8 @@ int print_cpuinfo(void)
puts("CPU: Allwinner A20 (SUN7I)\n");
#elif defined CONFIG_MACH_SUN8I
puts("CPU: Allwinner A23 (SUN8I)\n");
+#elif defined CONFIG_MACH_SUN9I
+ puts("CPU: Allwinner A80 (SUN9I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
@@ -82,6 +85,8 @@ int sunxi_get_sid(unsigned int *sid)
#else
return -ENODEV;
#endif
+#elif defined CONFIG_MACH_SUN9I
+ return -ENODEV; /* Not supported yet */
#else
int i;
@@ -14,10 +14,20 @@
*/
ENTRY(save_boot_params)
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN8I
+ defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN9I
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #(1<<6)
mcr p15, 0, r0, c1, c0, 1
#endif
+#if defined CONFIG_MACH_SUN9I
+ /*
+ * Dark magic poke of some register in the SYS_CTRL region.
+ * Allwinners own u-boot does this and without this u-boot causes a
+ * CPU / system reset as soon as it loads.
+ */
+ ldr r0, =0x008000e0
+ ldr r1, =0x16aa0001
+ str r1, [r0]
+#endif
bx lr
ENDPROC(save_boot_params)
@@ -174,6 +174,9 @@ enum sunxi_gpio_number {
#define SUN4I_GPH22_SDC1 5
+#define SUN9I_GPH12_UART0_TX 2
+#define SUN9I_GPH13_UART0_RX 2
+
#define SUN6I_GPH20_UART0_TX 2
#define SUN6I_GPH21_UART0_RX 2
@@ -31,6 +31,10 @@ config MACH_SUN8I
select CPU_V7
select SUPPORT_SPL
+config MACH_SUN9I
+ bool "sun9i (Allwinner A80)"
+ select CPU_V7
+
endchoice
if MACH_SUN6I || MACH_SUN8I
@@ -56,6 +60,7 @@ config SYS_CONFIG_NAME
default "sun6i" if MACH_SUN6I
default "sun7i" if MACH_SUN7I
default "sun8i" if MACH_SUN8I
+ default "sun9i" if MACH_SUN9I
choice
prompt "Board"
new file mode 100644
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Configuration settings for the Allwinner A80 (sun9i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A80 specific configuration
+ */
+
+#define CONFIG_SYS_PROMPT "sun9i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
Add initial sun9i (A80) support, only uart + mmc are supported for now. Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c | 4 ++++ arch/arm/cpu/armv7/sunxi/cpu_info.c | 5 +++++ arch/arm/cpu/armv7/sunxi/lowlevel_init.S | 12 +++++++++++- arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ board/sunxi/Kconfig | 5 +++++ include/configs/sun9i.h | 23 +++++++++++++++++++++++ 7 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 include/configs/sun9i.h