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Wed, 14 Jan 2015 22:44:42 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NI6003XG63WHL60@mmp2.samsung.com>; Wed, 14 Jan 2015 22:44:42 +0900 (KST) From: Akshay Saraswat To: u-boot@lists.denx.de Date: Wed, 14 Jan 2015 19:05:35 +0530 Message-id: <1421242536-4209-4-git-send-email-akshay.s@samsung.com> X-Mailer: git-send-email 2.2.0 In-reply-to: <1421242536-4209-1-git-send-email-akshay.s@samsung.com> References: <1421242536-4209-1-git-send-email-akshay.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrDLMWRmVeSWpSXmKPExsWyRsSkWvdU0bYQg3eT9SxO/XnMaHHjVxur xYt7F1ksOo60MFp827KN0eLt3k52BzaP2Q0XWTzO3tnB6NG3ZRVjAHMUl01Kak5mWWqRvl0C V8biqyeZCv5KVTx8dYetgfGVaBcjB4eEgInEopaALkZOIFNM4sK99WxdjFwcQgJLGSVuzzjM DpEwkTjQuQ3MFhKYziix+QY/RNEEJokPh0+ygCTYBHQkti/5DlYkIiAh8av/KiNIEbNAK6PE zRfrGUESwgLOEov3dbKAbGYRUJU4NaMOJMwLFP7eOJ0FYpmcxJZbj8DmcAq4SPzeuRBqsbPE zaZWsOskBJrZJU60ngFLsAgISHybfIgF4htZiU0HmCHmSEocXHGDZQKj8AJGhlWMoqkFyQXF SelFhnrFibnFpXnpesn5uZsYgYF8+t+z3h2Mtw9YH2IU4GBU4uF1OLI1RIg1say4MvcQoynQ honMUqLJ+cB4ySuJNzQ2M7IwNTE1NjK3NFMS51WU+hksJJCeWJKanZpakFoUX1Sak1p8iJGJ g1OqgXGW5df8uB1hf6z6ttm3H60tvv/ROiEsxPfmjG2mvIlLfaW8D0lo/7v+5np2/u+sbZ/k i3lf/C08MaNgV9brPHm+fdaLqw8ZLnswubRDOETtWdiXHQqMQfLT2kLSFz44vZunyaX98FvW x2Veza9uTFjIy6a9t/4oe8K0+Ac/TQ8elv3X1Hf/9A4lluKMREMt5qLiRAAstfUmXwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsVy+t9jQd1TRdtCDKatVbM49ecxo8WNX22s Fi/uXWSx6DjSwmjxbcs2Rou3ezvZHdg8ZjdcZPE4e2cHo0ffllWMAcxRDYw2GamJKalFCql5 yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUCblRTKEnNKgUIBicXFSvp2 mCaEhrjpWsA0Ruj6hgTB9RgZoIGENYwZi6+eZCr4K1Xx8NUdtgbGV6JdjJwcEgImEgc6t7FD 2GISF+6tZwOxhQSmM0psvsHfxcgFZE9gkvhw+CQLSIJNQEdi+5LvYA0iAhISv/qvMoIUMQu0 MkrcfLGeESQhLOAssXhfJ1ADBweLgKrEqRl1IGFeoPD3xuksEMvkJLbcegQ2h1PAReL3zoXs EIudJW42tbJNYORdwMiwilE0tSC5oDgpPddQrzgxt7g0L10vOT93EyM4Up5J7WBc2WBxiFGA g1GJh9fhyNYQIdbEsuLK3EOMEhzMSiK8aXLbQoR4UxIrq1KL8uOLSnNSiw8xmgIdNZFZSjQ5 HxjFeSXxhsYm5qbGppYmFiZmlkrivEr2bSFCAumJJanZqakFqUUwfUwcnFINjCcuLNFWt8tO 0t58Rv2EWf4MHe80yRY+rsNVjg6WuvGNEyeYaL0rCMttbZpU6T1JUKeg+uv7buOAv46zjy/W DW2sv3E7jXvGVyFL1ltaG5vaf3boL1hooentvi/t5ZQdB8sDHSW6zAVFD698k/DpqYN/M3No CaMfe2SDn0fixuZD6YuUZwkrsRRnJBpqMRcVJwIAR8yh8qoCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: jh80.chung@samsung.com, Akshay Saraswat Subject: [U-Boot] [PATCH 3/4] Exynos5: Use clock_get_periph_rate generic API X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Replacing SoC and peripheral specific function calls with generic clock_get_periph_rate calls to get the peripheral clocks. Signed-off-by: Akshay Saraswat --- arch/arm/cpu/armv7/exynos/clock.c | 60 +++++++++++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 9ac4579..9c719aa 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -406,10 +406,13 @@ static unsigned long exynos5_get_periph_rate(int peripheral) break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); + break; case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: src = readl(&clk->src_fsys); - div = readl(&clk->div_fsys1); + div = readl(&clk->div_fsys2); break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -450,8 +453,7 @@ static unsigned long exynos5_get_periph_rate(int peripheral) sub_div = (div >> bit_info->div_bit) & 0xf; sub_clk = sclk / (sub_div + 1); - /* Pre-ratio clock division for SDMMC0 and 2 */ - if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { + if (bit_info->prediv_bit >= 0) { div = (div >> bit_info->prediv_bit) & 0xff; return sub_clk / (div + 1); } @@ -1766,7 +1768,7 @@ unsigned long get_arm_clk(void) unsigned long get_i2c_clk(void) { if (cpu_is_exynos5()) { - return exynos5_get_i2c_clk(); + return clock_get_periph_rate(PERIPH_ID_I2C0); } else if (cpu_is_exynos4()) { return exynos4_get_i2c_clk(); } else { @@ -1778,8 +1780,6 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); } else { if (proid_is_exynos4412()) @@ -1790,10 +1790,28 @@ unsigned long get_pwm_clk(void) unsigned long get_uart_clk(int dev_index) { + enum periph_id id; + + switch (dev_index) { + case 0: + id = PERIPH_ID_UART0; + break; + case 1: + id = PERIPH_ID_UART1; + break; + case 2: + id = PERIPH_ID_UART2; + break; + case 3: + id = PERIPH_ID_UART3; + break; + default: + debug("%s: invalid UART index %d", __func__, dev_index); + return -1; + } + if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_uart_clk(dev_index); - return exynos5_get_uart_clk(dev_index); + return clock_get_periph_rate(id); } else { if (proid_is_exynos4412()) return exynos4x12_get_uart_clk(dev_index); @@ -1803,10 +1821,28 @@ unsigned long get_uart_clk(int dev_index) unsigned long get_mmc_clk(int dev_index) { + enum periph_id id; + + switch (dev_index) { + case 0: + id = PERIPH_ID_SDMMC0; + break; + case 1: + id = PERIPH_ID_SDMMC1; + break; + case 2: + id = PERIPH_ID_SDMMC2; + break; + case 3: + id = PERIPH_ID_SDMMC3; + break; + default: + debug("%s: invalid MMC index %d", __func__, dev_index); + return -1; + } + if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_mmc_clk(dev_index); - return exynos5_get_mmc_clk(dev_index); + return clock_get_periph_rate(id); } else { return exynos4_get_mmc_clk(dev_index); }