From patchwork Sat Jan 3 14:40:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 425116 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1276914007F for ; Sun, 4 Jan 2015 01:41:08 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 89FC44B669; Sat, 3 Jan 2015 15:40:59 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qenggb+oCuwg; Sat, 3 Jan 2015 15:40:59 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 250244B692; Sat, 3 Jan 2015 15:40:56 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DE0644B659 for ; Sat, 3 Jan 2015 15:40:51 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tyHqw5smovq9 for ; Sat, 3 Jan 2015 15:40:51 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f50.google.com (mail-pa0-f50.google.com [209.85.220.50]) by theia.denx.de (Postfix) with ESMTPS id 6B2464B670 for ; Sat, 3 Jan 2015 15:40:47 +0100 (CET) Received: by mail-pa0-f50.google.com with SMTP id bj1so25814667pad.9 for ; Sat, 03 Jan 2015 06:40:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cy38nj2m0P624XAkY21O3Qlp7rU7TrkA+bB6fusIUTk=; b=SX60lcwJ4jqQm/aBjKNKMzdbgTUpoX6rkpqC87BSpWjhhMwchNCwn2iICqxSWayD5q EX/Gie+R2X8StbR905ph+l+oy++QqT5BrIG3BKNqTh5UACRRxcsrr71ZnfX+0PWpwKmU aT6TOPanDbttb/u8X9ZQC3kSBc/lIk3SJmOhVodNwLW/8Aa4Iyuq27o4Zcc7KRwq8KHN fOcnPBEO9Cc3tt5drCcfLJLk69N0QFLa+t+4uWTqqGlBj+mIJesKVUNe1TElbuOW0fSz A7xR3VHrvchU6Tn7xahEH9Vg1ETLHVooVxVhSI0D6wI9zVFc+waX8HiBredLgnoQQFQy S/qA== X-Received: by 10.68.111.100 with SMTP id ih4mr58985994pbb.12.1420296046079; Sat, 03 Jan 2015 06:40:46 -0800 (PST) Received: from localhost ([106.120.101.38]) by mx.google.com with ESMTPSA id z5sm49409345pbt.89.2015.01.03.06.40.44 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sat, 03 Jan 2015 06:40:45 -0800 (PST) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Sat, 3 Jan 2015 22:40:25 +0800 Message-Id: <1420296026-8764-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1420296026-8764-1-git-send-email-bmeng.cn@gmail.com> References: <1420296026-8764-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 2/3] x86: Allow a hardcoded TSC frequency provided by Kconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de By default U-Boot automatically calibrates TSC running frequency via MSR and PIT. The calibration may not work on every x86 processor, so a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to allow bypassing the calibration and assign a hardcoded TSC frequency CONFIG_TSC_FREQ_IN_MHZ. Normally the bypass should be turned on in a simulation environment like qemu. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/Kconfig | 18 ++++++++++++++++++ arch/x86/lib/tsc_timer.c | 8 ++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ebf72b3..9c11f0e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -317,6 +317,24 @@ config FRAMEBUFFER_VESA_MODE endmenu +config TSC_CALIBRATION_BYPASS + bool "Bypass TSC calibration" + default n + help + By default U-Boot automatically calibrates TSC running frequency via + MSR and PIT. If the calibration does not work on your board, select + this option and provide a hardcoded TSC running frequency below. + + Normally this option should be turned on in a simulation environment + like qemu. + +config TSC_FREQ_IN_MHZ + int "TSC running frequency in MHz" + depends on TSC_CALIBRATION_BYPASS + default 1000 + help + The running frequency in MHz of TSC + source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/queensbay/Kconfig" diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c index fb9afed..7f5ba2c 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/arch/x86/lib/tsc_timer.c @@ -78,7 +78,7 @@ static int match_cpu(u8 family, u8 model) * * Returns the calibration value or 0 if MSR calibration failed. */ -static unsigned long try_msr_calibrate_tsc(void) +static unsigned long __maybe_unused try_msr_calibrate_tsc(void) { u32 lo, hi, ratio, freq_id, freq; unsigned long res; @@ -199,7 +199,7 @@ static inline int pit_expect_msb(unsigned char val, u64 *tscp, #define MAX_QUICK_PIT_MS 50 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) -static unsigned long quick_pit_calibrate(void) +static unsigned long __maybe_unused quick_pit_calibrate(void) { int i; u64 tsc, delta; @@ -306,6 +306,9 @@ unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void) if (gd->arch.tsc_mhz) return gd->arch.tsc_mhz; +#ifdef CONFIG_TSC_CALIBRATION_BYPASS + fast_calibrate = CONFIG_TSC_FREQ_IN_MHZ; +#else fast_calibrate = try_msr_calibrate_tsc(); if (!fast_calibrate) { @@ -313,6 +316,7 @@ unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void) if (!fast_calibrate) panic("TSC frequency is ZERO"); } +#endif gd->arch.tsc_mhz = fast_calibrate; return fast_calibrate;