From patchwork Sun Dec 28 02:20:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 424284 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5A4EB1400D5 for ; Sun, 28 Dec 2014 13:23:15 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6CF884B713; Sun, 28 Dec 2014 03:22:40 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ix1T-o5TLYHS; Sun, 28 Dec 2014 03:22:40 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0D54F4B715; Sun, 28 Dec 2014 03:21:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E0F874B688 for ; Sun, 28 Dec 2014 03:21:25 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SMTQQbNaKVBb for ; Sun, 28 Dec 2014 03:21:25 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yh0-f74.google.com (mail-yh0-f74.google.com [209.85.213.74]) by theia.denx.de (Postfix) with ESMTPS id 457944B699 for ; Sun, 28 Dec 2014 03:21:20 +0100 (CET) Received: by mail-yh0-f74.google.com with SMTP id 29so570444yhl.5 for ; Sat, 27 Dec 2014 18:21:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BgXwBn+D68A7kR2HVEgAwFqRDIxCINACJu57X1j9wjw=; b=C+zd5XhrygvbH/+QUe3rR7+qPE3bIJ3/ttL+Z8pehMZ0ai6083uKWOETdktzbtrh+u k0IzE0Fz5BS5ubBYEd1DvF5uF49hB5ZwDfslouAsYsdrUzRKr+K/RJ4tbf3iBQuR834A T+vOvZoVS6T2BnhEPKhzDyebqTorzEXthnZ7IrMP8kHAi6Mp+meYag4yj9795oqxqyIL CIipXLBOTRkT3EW1DYybhD31jNWuuzOMypYkUmFXf89T2TCKh/aIIPsNR4KLMuOzZ1pg BfZ8NgrYsmp/sz2lYvoIGrB7EhZT5i17Ka1xx+GWjQAVt4ASLe2k77o0fiNCV0+3DEN3 dtCQ== X-Gm-Message-State: ALoCoQk9Ij7d5P5Q8UDwrDg3HYJiRNrEfiWRVHGqUcQOHo5RjT2l8LNwx5ZyTBP5XNtcjd1TGzLX X-Received: by 10.236.43.202 with SMTP id l50mr29293736yhb.23.1419733279207; Sat, 27 Dec 2014 18:21:19 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id t7si76860yho.3.2014.12.27.18.21.18 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 27 Dec 2014 18:21:19 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id 4Jh41VEf.3; Sat, 27 Dec 2014 18:21:19 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 56DDC221590; Sat, 27 Dec 2014 19:21:18 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Sat, 27 Dec 2014 19:20:46 -0700 Message-Id: <1419733246-5612-23-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1419733246-5612-1-git-send-email-sjg@chromium.org> References: <1419733246-5612-1-git-send-email-sjg@chromium.org> Cc: Marek Vasut , Graeme Russ , Vadim Bendebury Subject: [U-Boot] [PATCH 22/22] x86: Add an 'mtrr' command to list and adjust MTRRs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de It is useful to be able to see the MTRR setup in U-Boot. Add a command to list the state of the variable MTRR registers and allow them to be changed. Update the documentation to list some of the available commands. This does not support fixed MTRRs as yet. Signed-off-by: Simon Glass --- common/Makefile | 1 + common/cmd_mtrr.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ doc/README.x86 | 18 ++++++- 3 files changed, 156 insertions(+), 1 deletion(-) create mode 100644 common/cmd_mtrr.c diff --git a/common/Makefile b/common/Makefile index c668a2f..39e4e5f 100644 --- a/common/Makefile +++ b/common/Makefile @@ -135,6 +135,7 @@ obj-$(CONFIG_CMD_MMC) += cmd_mmc.o obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o obj-$(CONFIG_MP) += cmd_mp.o obj-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o +obj-$(CONFIG_X86) += cmd_mtrr.o obj-$(CONFIG_CMD_NAND) += cmd_nand.o obj-$(CONFIG_CMD_NET) += cmd_net.o obj-$(CONFIG_CMD_ONENAND) += cmd_onenand.o diff --git a/common/cmd_mtrr.c b/common/cmd_mtrr.c new file mode 100644 index 0000000..7e0506b --- /dev/null +++ b/common/cmd_mtrr.c @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { + "Uncacheable", + "Combine", + "2", + "3", + "Through", + "Protect", + "Back", +}; + +static int do_mtrr_list(void) +{ + int i; + + printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", + "Mask ||", "Size ||"); + for (i = 0; i < MTRR_COUNT; i++) { + const char *type = "Invalid"; + uint64_t base, mask, size; + bool valid; + + base = native_read_msr(MTRR_PHYS_BASE_MSR(i)); + mask = native_read_msr(MTRR_PHYS_MASK_MSR(i)); + size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); + size |= (1 << 12) - 1; + size += 1; + valid = mask & MTRR_PHYS_MASK_VALID; + type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; + printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, + valid ? "Y" : "N", type, base, mask, size); + } + + return 0; +} + +static int do_mtrr_set(uint reg, int argc, char * const argv[]) +{ + const char *typename = argv[0]; + struct mtrr_state state; + uint32_t start, size; + uint64_t base, mask; + int i, type = -1; + bool valid; + + if (argc < 3) + return CMD_RET_USAGE; + for (i = 0; i < MTRR_TYPE_COUNT; i++) { + if (*typename == *mtrr_type_name[i]) + type = i; + } + if (type == -1) { + printf("Invalid type name %s\n", typename); + return CMD_RET_USAGE; + } + start = simple_strtoul(argv[1], NULL, 16); + size = simple_strtoul(argv[2], NULL, 16); + + base = start | type; + valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID; + mask = ~((uint64_t)size - 1); + mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; + if (valid) + mask |= MTRR_PHYS_MASK_VALID; + + printf("base=%llx, mask=%llx\n", base, mask); + mtrr_open(&state); + wrmsrl(MTRR_PHYS_BASE_MSR(reg), base); + wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); + mtrr_close(&state); + + return 0; +} + +static int mtrr_set_valid(int reg, bool valid) +{ + struct mtrr_state state; + uint64_t mask; + + mtrr_open(&state); + mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg)); + if (valid) + mask |= MTRR_PHYS_MASK_VALID; + else + mask &= ~MTRR_PHYS_MASK_VALID; + wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); + mtrr_close(&state); + + return 0; +} + +static int do_mtrr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *cmd; + uint reg; + + cmd = argv[1]; + if (argc < 2 || *cmd == 'l') + return do_mtrr_list(); + argc -= 2; + argv += 2; + if (argc <= 0) + return CMD_RET_USAGE; + reg = simple_strtoul(argv[0], NULL, 16); + if (reg >= MTRR_COUNT) { + printf("Invalid register number\n"); + return CMD_RET_USAGE; + } + if (*cmd == 'e') + return mtrr_set_valid(reg, true); + else if (*cmd == 'd') + return mtrr_set_valid(reg, false); + else if (*cmd == 's') + return do_mtrr_set(reg, argc - 1, argv + 1); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + mtrr, 6, 1, do_mtrr, + "Use x86 memory type range registers (32-bit only)", + "[list] - list current registers\n" + "set - set a register\n" + "\t is Uncacheable, Combine, Through, Protect, Back\n" + "disable - disable a register\n" + "ensable - enable a register" +); diff --git a/doc/README.x86 b/doc/README.x86 index 5fab044..6fbfb90 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -110,9 +110,25 @@ be turned on. Not every device on the board is configured via devie tree, but more and more devices will be added as time goes by. Check out the directory arch/x86/dts/ for these device tree source files. +Useful Commands +--------------- + +In keeping with the U-Boot philosophy of providing functions to check and +adjust internal settings, there are several x86-specific commands that may be +useful: + +hob - Display information about Firmware Support Package (FSP) Hand-off + Block. This is only available on platform which use FSP, mostly + Atom. +iod - Display I/O memory +iow - Write I/O memory +mtrr - List and set the Memory Type Range Registers (MTRR). These are used to + tell the CPU whether memory is cacheable and if so the cache write + mode to use. U-Boot sets up some reasonable values but you can + adjust then with this command. + TODO List --------- -- MTRR support (for performance) - Audio - Chrome OS verified boot - SMI and ACPI support, to provide platform info and facilities to Linux