diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 599b021..eab4514 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -10,20 +10,12 @@ choice
 config TARGET_ATC
 	bool "Support atc"
 
-config TARGET_CPU86
-	bool "Support CPU86"
-
-config TARGET_CPU87
-	bool "Support CPU87"
-
 config TARGET_KM82XX
 	bool "Support km82xx"
 
 endchoice
 
 source "board/atc/Kconfig"
-source "board/cpu86/Kconfig"
-source "board/cpu87/Kconfig"
 source "board/keymile/km82xx/Kconfig"
 
 endmenu
diff --git a/board/cpu86/Kconfig b/board/cpu86/Kconfig
deleted file mode 100644
index ac3ae98..0000000
--- a/board/cpu86/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CPU86
-
-config SYS_BOARD
-	default "cpu86"
-
-config SYS_CONFIG_NAME
-	default "CPU86"
-
-endif
diff --git a/board/cpu86/MAINTAINERS b/board/cpu86/MAINTAINERS
deleted file mode 100644
index 06bdd0d..0000000
--- a/board/cpu86/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-CPU86 BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/cpu86/
-F:	include/configs/CPU86.h
-F:	configs/CPU86_defconfig
-F:	configs/CPU86_ROMBOOT_defconfig
diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile
deleted file mode 100644
index da83afd..0000000
--- a/board/cpu86/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= cpu86.o flash.o
diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c
deleted file mode 100644
index 9292910..0000000
--- a/board/cpu86/cpu86.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include "cpu86.h"
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
-	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
-	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
-	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
-	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
-	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
-	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
-	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
-	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
-	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
-	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
-	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
-	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
-	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
-	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
-	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
-	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
-	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
-	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
-	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
-	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
-	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
-	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
-	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
-	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
-	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
-	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
-	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
-	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
-	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
-	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
-	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
-    },
-
-    /* Port B configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
-    },
-
-    /* Port C */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
-	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
-	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
-	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
-	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
-	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
-	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
-	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
-	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
-	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
-	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
-	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
-	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
-	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
-    },
-
-    /* Port D */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
-	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
-	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
-	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
-	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
-	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
-	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
-#if defined(CONFIG_SYS_I2C_SOFT)
-	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
-	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#else /* normal I/O port pins */
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#endif
-#endif
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
-    }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
-	printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
-			  ulong orx, volatile uchar * base)
-{
-	volatile uchar c = 0xff;
-	volatile uint *sdmr_ptr;
-	volatile uint *orx_ptr;
-	ulong maxsize, size;
-	int i;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (1 + (~orx | 0x7fff)) / 2;
-
-	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
-	 * we are configuring CS1 if base != 0
-	 */
-	sdmr_ptr = &memctl->memc_psdmr;
-	orx_ptr = &memctl->memc_or2;
-
-	*orx_ptr = orx;
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
-	*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*base = c;
-
-	size = get_ram_size((long *)base, maxsize);
-
-	*orx_ptr = orx | ~(size - 1);
-
-	return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong size8, size9;
-#endif
-	long psize;
-
-	psize = 32 * 1024 * 1024;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	/* 60x SDRAM setup:
-	 */
-	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
-			  (uchar *) CONFIG_SYS_SDRAM_BASE);
-	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
-			  (uchar *) CONFIG_SYS_SDRAM_BASE);
-
-	if (size8 < size9) {
-		psize = size9;
-		printf ("(60x:9COL) ");
-	} else {
-		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
-				  (uchar *) CONFIG_SYS_SDRAM_BASE);
-		printf ("(60x:8COL) ");
-	}
-
-#endif	/* CONFIG_SYS_RAMBOOT */
-
-	icache_enable ();
-
-	return (psize);
-}
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
-	doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h
deleted file mode 100644
index ca0c39f..0000000
--- a/board/cpu86/cpu86.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __BOARD_CPU86__
-#define __BOARD_CPU86__
-
-#include <config.h>
-
-#define REG8(x)			(*(volatile unsigned char *)(x))
-
-/* CPU86 register definitions */
-#define CPU86_VME_EAC		REG8(CONFIG_SYS_BCRS_BASE + 0x00)
-#define CPU86_VME_SAC		REG8(CONFIG_SYS_BCRS_BASE + 0x01)
-#define CPU86_VME_MAC		REG8(CONFIG_SYS_BCRS_BASE + 0x02)
-#define CPU86_BCR		REG8(CONFIG_SYS_BCRS_BASE + 0x03)
-#define CPU86_BSR		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
-#define CPU86_WDOG_RPORT	REG8(CONFIG_SYS_BCRS_BASE + 0x05)
-#define CPU86_MBOX_IRQ		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
-#define CPU86_REV		REG8(CONFIG_SYS_BCRS_BASE + 0x07)
-#define CPU86_VME_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x80)
-#define CPU86_VME_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x81)
-#define CPU86_LOCAL_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x82)
-#define CPU86_LOCAL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x83)
-#define CPU86_PMCL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x84)
-
-/* Board Control Register bits */
-#define CPU86_BCR_FWPT		0x01
-#define CPU86_BCR_FWRE		0x02
-
-#endif /* __BOARD_CPU86__ */
diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c
deleted file mode 100644
index b99a9a0..0000000
--- a/board/cpu86/flash.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Flash Routines for Intel devices
- *
- *--------------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "cpu86.h"
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_int_get_size (volatile unsigned long *baseaddr,
-					  flash_info_t * info)
-{
-	short i;
-	unsigned long flashtest_h, flashtest_l;
-
-	info->sector_count = info->size = 0;
-	info->flash_id = FLASH_UNKNOWN;
-
-	/* Write identify command sequence and test FLASH answer
-	 */
-	baseaddr[0] = 0x00900090;
-	baseaddr[1] = 0x00900090;
-
-	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
-	flashtest_l = baseaddr[1];
-
-	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
-		return (0);		/* no or unknown flash	*/
-
-	flashtest_h = baseaddr[2];	/* device ID	        */
-	flashtest_l = baseaddr[3];
-
-	if (flashtest_h != flashtest_l)
-		return (0);
-
-	switch (flashtest_h) {
-	case INTEL_ID_28F160C3B:
-		info->flash_id = FLASH_28F160C3B;
-		info->sector_count = 39;
-		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
-		break;
-	case INTEL_ID_28F160F3B:
-		info->flash_id = FLASH_28F160F3B;
-		info->sector_count = 39;
-		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
-		break;
-	default:
-		return (0);			/* no or unknown flash	*/
-	}
-
-	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
-
-	if (info->flash_id & FLASH_BTYPE) {
-		volatile unsigned long *tmp = baseaddr;
-
-		/* set up sector start adress table (bottom sector type)
-		 * AND unlock the sectors (if our chip is 160C3)
-		 */
-		for (i = 0; i < info->sector_count; i++) {
-			if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) {
-				tmp[0] = 0x00600060;
-				tmp[1] = 0x00600060;
-				tmp[0] = 0x00D000D0;
-				tmp[1] = 0x00D000D0;
-			}
-			info->start[i] = (uint) tmp;
-			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
-		}
-	}
-
-	memset (info->protect, 0, info->sector_count);
-
-	baseaddr[0] = 0x00FF00FF;
-	baseaddr[1] = 0x00FF00FF;
-
-	return (info->size);
-}
-
-static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
-{
-	short i;
-	uchar vendor, devid;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0xAA;
-	addr[0x02AA] = 0x55;
-	addr[0x0555] = 0x90;
-
-	udelay(1000);
-
-	vendor = addr[0];
-	devid = addr[1] & 0xff;
-
-	/* only support AMD */
-	if (vendor != 0x01) {
-		return 0;
-	}
-
-	vendor &= 0xf;
-	devid &= 0xff;
-
-	if (devid == AMD_ID_F040B) {
-		info->flash_id     = vendor << 16 | devid;
-		info->sector_count = 8;
-		info->size         = info->sector_count * 0x10000;
-	}
-	else if (devid == AMD_ID_F080B) {
-		info->flash_id     = vendor << 16 | devid;
-		info->sector_count = 16;
-		info->size         = 4 * info->sector_count * 0x10000;
-	}
-	else if (devid == AMD_ID_F016D) {
-		info->flash_id     = vendor << 16 | devid;
-		info->sector_count = 32;
-		info->size         = 4 * info->sector_count * 0x10000;
-	}
-	else {
-		printf ("## Unknown Flash Type: %02x\n", devid);
-		return 0;
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* sector base address */
-		info->start[i] = base + i * (info->size / info->sector_count);
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned char *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (vu_char *)info->start[0];
-		addr[0] = 0xF0; /* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-	unsigned long size_b0 = 0;
-	unsigned long size_b1 = 0;
-	int i;
-
-	/* Init: no FLASHes known
-	 */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Disable flash protection */
-	CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
-
-	/* Static FLASH Bank configuration here (only one bank) */
-
-	size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-	size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
-
-	if (size_b0 > 0 || size_b1 > 0) {
-
-		printf("(");
-
-		if (size_b0 > 0) {
-			puts ("Bank#1 - ");
-			print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
-		}
-
-		if (size_b1 > 0) {
-			puts ("Bank#2 - ");
-			print_size (size_b1, ") ");
-		}
-	}
-	else {
-		printf ("## No FLASH found.\n");
-		return 0;
-	}
-	/* protect monitor and environment sectors
-	 */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
-	if (size_b1) {
-		/* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
-		 * but we shouldn't protect it.
-		 */
-
-		flash_protect  (FLAG_PROTECT_SET,
-				CONFIG_SYS_MONITOR_BASE,
-				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
-		);
-	}
-#else
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
-	);
-#endif
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
-	if (size_b1) {
-		flash_protect (FLAG_PROTECT_SET,
-				CONFIG_ENV_ADDR,
-				CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
-	}
-# else
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-# endif
-#endif
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch ((info->flash_id >> 16) & 0xff) {
-	case 0x89:
-		printf ("INTEL ");
-		break;
-	case 0x1:
-		printf ("AMD ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F160C3B:
-		printf ("28F160C3B (16 Mbit, bottom sector)\n");
-		break;
-	case FLASH_28F160F3B:
-		printf ("28F160F3B (16 Mbit, bottom sector)\n");
-		break;
-	case AMD_ID_F040B:
-		printf ("AM29F040B (4 Mbit)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	if (info->size < 0x100000)
-		printf ("  Size: %ld KB in %d Sectors\n",
-				info->size >> 10, info->sector_count);
-	else
-		printf ("  Size: %ld MB in %d Sectors\n",
-				info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	vu_char *addr = (vu_char *)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-				prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Check the type of erased flash
-	 */
-	if (info->flash_id >> 16 == 0x1) {
-		/* Erase AMD flash
-		 */
-		l_sect = -1;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr[0x0555] = 0xAA;
-		addr[0x02AA] = 0x55;
-		addr[0x0555] = 0x80;
-		addr[0x0555] = 0xAA;
-		addr[0x02AA] = 0x55;
-
-		/* wait at least 80us - let's wait 1 ms */
-		udelay (1000);
-
-		/* Start erase on unprotected sectors */
-		for (sect = s_first; sect<=s_last; sect++) {
-			if (info->protect[sect] == 0) { /* not protected */
-				addr = (vu_char *)(info->start[sect]);
-				addr[0] = 0x30;
-				l_sect = sect;
-			}
-		}
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* wait at least 80us - let's wait 1 ms */
-		udelay (1000);
-
-		/*
-		 * We wait for the last triggered sector
-		 */
-		if (l_sect < 0)
-			goto AMD_DONE;
-
-		start = get_timer (0);
-		last  = start;
-		addr = (vu_char *)(info->start[l_sect]);
-		while ((addr[0] & 0x80) != 0x80) {
-			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-				printf ("Timeout\n");
-				return 1;
-			}
-			/* show that we're waiting */
-			if ((now - last) > 1000) {      /* every second */
-				serial_putc ('.');
-				last = now;
-			}
-		}
-
-AMD_DONE:
-		/* reset to read mode */
-		addr = (volatile unsigned char *)info->start[0];
-		addr[0] = 0xF0;     /* reset bank */
-
-	} else {
-		/* Erase Intel flash
-		 */
-
-		/* Start erase on unprotected sectors
-		 */
-		for (sect = s_first; sect <= s_last; sect++) {
-			volatile ulong *addr =
-				(volatile unsigned long *) info->start[sect];
-
-			start = get_timer (0);
-			last = start;
-			if (info->protect[sect] == 0) {
-			/* Disable interrupts which might cause a timeout here
-			 */
-				flag = disable_interrupts ();
-
-				/* Erase the block
-				 */
-				addr[0] = 0x00200020;
-				addr[1] = 0x00200020;
-				addr[0] = 0x00D000D0;
-				addr[1] = 0x00D000D0;
-
-				/* re-enable interrupts if necessary
-				 */
-				if (flag)
-					enable_interrupts ();
-
-				/* wait at least 80us - let's wait 1 ms
-				 */
-				udelay (1000);
-
-				last = start;
-				while ((addr[0] & 0x00800080) != 0x00800080 ||
-				   (addr[1] & 0x00800080) != 0x00800080) {
-					if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-						printf ("Timeout (erase suspended!)\n");
-						/* Suspend erase
-						 */
-						addr[0] = 0x00B000B0;
-						addr[1] = 0x00B000B0;
-						goto DONE;
-					}
-					/* show that we're waiting
-					 */
-					if ((now - last) > 1000) {	/* every second */
-						serial_putc ('.');
-						last = now;
-					}
-				}
-				if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
-					printf ("*** ERROR: erase failed!\n");
-					goto DONE;
-				}
-			}
-			/* Clear status register and reset to read mode
-			 */
-			addr[0] = 0x00500050;
-			addr[1] = 0x00500050;
-			addr[0] = 0x00FF00FF;
-			addr[1] = 0x00FF00FF;
-		}
-	}
-
-	printf (" done\n");
-
-DONE:
-	return 0;
-}
-
-static int write_word (flash_info_t *, volatile unsigned long *, ulong);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong v;
-	int i, l, rc, cc = cnt, res = 0;
-
-	if (info->flash_id >> 16 == 0x1) {
-
-		/* Write to AMD 8-bit flash
-		 */
-		while (cnt > 0) {
-			if ((rc = write_byte(info, addr, *src)) != 0) {
-				return (rc);
-			}
-			addr++;
-			src++;
-			cnt--;
-		}
-
-		return (0);
-	} else {
-
-		/* Write to Intel 64-bit flash
-		 */
-		for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
-			l = (addr & 3);
-			addr &= ~3;
-
-			for (i = 0; i < 4; i++) {
-				v = (v << 8) + (i < l || i - l >= cc ?
-					*((unsigned char *) addr + i) : *src++);
-			}
-
-			if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
-				break;
-		}
-	}
-
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, volatile unsigned long *addr,
-					   ulong data)
-{
-	int flag, res = 0;
-	ulong start;
-
-	/* Check if Flash is (sufficiently) erased
-	 */
-	if ((*addr & data) != data)
-		return (2);
-
-	/* Disable interrupts which might cause a timeout here
-	 */
-	flag = disable_interrupts ();
-
-	*addr = 0x00400040;
-	*addr = data;
-
-	/* re-enable interrupts if necessary
-	 */
-	if (flag)
-		enable_interrupts ();
-
-	start = get_timer (0);
-	while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			/* Suspend program
-			 */
-			*addr = 0x00B000B0;
-			res = 1;
-			goto OUT;
-		}
-	}
-
-	if (*addr & 0x00220022) {
-		printf ("*** ERROR: program failed!\n");
-		res = 1;
-	}
-
-OUT:
-	/* Clear status register and reset to read mode
-	 */
-	*addr = 0x00500050;
-	*addr = 0x00FF00FF;
-
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a byte to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte (flash_info_t *info, ulong dest, uchar data)
-{
-	vu_char *addr = (vu_char *)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_char *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0xAA;
-	addr[0x02AA] = 0x55;
-	addr[0x0555] = 0xA0;
-
-	*((vu_char *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/cpu87/Kconfig b/board/cpu87/Kconfig
deleted file mode 100644
index a4f2768..0000000
--- a/board/cpu87/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CPU87
-
-config SYS_BOARD
-	default "cpu87"
-
-config SYS_CONFIG_NAME
-	default "CPU87"
-
-endif
diff --git a/board/cpu87/MAINTAINERS b/board/cpu87/MAINTAINERS
deleted file mode 100644
index 32804ea..0000000
--- a/board/cpu87/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-CPU87 BOARD
-#M:	-
-S:	Maintained
-F:	board/cpu87/
-F:	include/configs/CPU87.h
-F:	configs/CPU87_defconfig
-F:	configs/CPU87_ROMBOOT_defconfig
diff --git a/board/cpu87/Makefile b/board/cpu87/Makefile
deleted file mode 100644
index 0d59bbb..0000000
--- a/board/cpu87/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= cpu87.o flash.o
diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
deleted file mode 100644
index 01f90d2..0000000
--- a/board/cpu87/cpu87.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include "cpu87.h"
-#include <pci.h>
-#include <netdev.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
-	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
-	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
-	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
-	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
-	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
-	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
-	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
-	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
-	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
-	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
-	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
-	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
-	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
-	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
-	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
-	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
-	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
-	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
-	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
-	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
-	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
-	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
-	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
-	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
-	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
-	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
-	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
-	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
-	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
-	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
-	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
-    },
-
-    /* Port B configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
-    },
-
-    /* Port C */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
-	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
-	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
-	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
-	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
-	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
-	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
-	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
-	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
-	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
-	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
-	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
-	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
-	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
-    },
-
-    /* Port D */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
-	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
-	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
-	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
-	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
-	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
-	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
-#if defined(CONFIG_SYS_I2C_SOFT)
-	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
-	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#else /* normal I/O port pins */
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#endif
-#endif
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
-    }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
-	printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
-			  ulong orx, volatile uchar * base)
-{
-	volatile uchar c = 0xff;
-	volatile uint *sdmr_ptr;
-	volatile uint *orx_ptr;
-	ulong maxsize, size;
-	int i;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (1 + (~orx | 0x7fff)) / 2;
-
-	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
-	 * we are configuring CS1 if base != 0
-	 */
-	sdmr_ptr = &memctl->memc_psdmr;
-	orx_ptr = &memctl->memc_or2;
-
-	*orx_ptr = orx;
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
-	*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*base = c;
-
-	size = get_ram_size((long *)base, maxsize);
-
-	*orx_ptr = orx | ~(size - 1);
-
-	return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong size8, size9, size10;
-#endif
-	long psize;
-
-	psize = 32 * 1024 * 1024;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	/* 60x SDRAM setup:
-	 */
-	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
-			  (uchar *) CONFIG_SYS_SDRAM_BASE);
-
-	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
-			  (uchar *) CONFIG_SYS_SDRAM_BASE);
-
-	size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL,
-			  (uchar *) CONFIG_SYS_SDRAM_BASE);
-
-	psize = max(size8,max(size9,size10));
-
-	if (psize == size8) {
-		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
-				  (uchar *) CONFIG_SYS_SDRAM_BASE);
-		printf ("(60x:8COL) ");
-	} else if (psize == size9){
-		psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
-				  (uchar *) CONFIG_SYS_SDRAM_BASE);
-		printf ("(60x:9COL) ");
-	} else
-		printf ("(60x:10COL) ");
-
-#endif	/* CONFIG_SYS_RAMBOOT */
-
-	icache_enable ();
-
-	return (psize);
-}
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
-	doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
-
-#ifdef	CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc8250_init(&hose);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h
deleted file mode 100644
index 45cb853..0000000
--- a/board/cpu87/cpu87.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __BOARD_CPU87__
-#define __BOARD_CPU87__
-
-#include <config.h>
-
-#define REG8(x)			(*(volatile unsigned char *)(x))
-
-/* CPU86 register definitions */
-#define CPU86_VME_EAC		REG8(CONFIG_SYS_BCRS_BASE + 0x00)
-#define CPU86_VME_SAC		REG8(CONFIG_SYS_BCRS_BASE + 0x01)
-#define CPU86_VME_MAC		REG8(CONFIG_SYS_BCRS_BASE + 0x02)
-#define CPU86_BCR		REG8(CONFIG_SYS_BCRS_BASE + 0x03)
-#define CPU86_BSR		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
-#define CPU86_WDOG_RPORT	REG8(CONFIG_SYS_BCRS_BASE + 0x05)
-#define CPU86_MBOX_IRQ		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
-#define CPU86_REV		REG8(CONFIG_SYS_BCRS_BASE + 0x07)
-#define CPU86_VME_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x80)
-#define CPU86_VME_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x81)
-#define CPU86_LOCAL_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x82)
-#define CPU86_LOCAL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x83)
-#define CPU86_PMCL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x84)
-
-/* Board Control Register bits */
-#define CPU86_BCR_FWPT		0x01
-#define CPU86_BCR_FWRE		0x02
-
-#endif /* __BOARD_CPU87__ */
diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c
deleted file mode 100644
index 96ba7d9..0000000
--- a/board/cpu87/flash.c
+++ /dev/null
@@ -1,608 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Flash Routines for Intel devices
- *
- *--------------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "cpu87.h"
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_int_get_size (volatile unsigned long *baseaddr,
-					  flash_info_t * info)
-{
-	short i;
-	unsigned long flashtest_h, flashtest_l;
-
-	info->sector_count = info->size = 0;
-	info->flash_id = FLASH_UNKNOWN;
-
-	/* Write identify command sequence and test FLASH answer
-	 */
-	baseaddr[0] = 0x00900090;
-	baseaddr[1] = 0x00900090;
-
-	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
-	flashtest_l = baseaddr[1];
-
-	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
-		return (0);		/* no or unknown flash	*/
-
-	flashtest_h = baseaddr[2];	/* device ID	        */
-	flashtest_l = baseaddr[3];
-
-	if (flashtest_h != flashtest_l)
-		return (0);
-
-	switch (flashtest_h) {
-	case INTEL_ID_28F160C3B:
-		info->flash_id = FLASH_28F160C3B;
-		info->sector_count = 39;
-		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
-		break;
-	case INTEL_ID_28F160F3B:
-		info->flash_id = FLASH_28F160F3B;
-		info->sector_count = 39;
-		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
-		break;
-	case INTEL_ID_28F640C3B:
-		info->flash_id = FLASH_28F640C3B;
-		info->sector_count = 135;
-		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
-		break;
-	default:
-		return (0);			/* no or unknown flash	*/
-	}
-
-	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
-
-	if (info->flash_id & FLASH_BTYPE) {
-		volatile unsigned long *tmp = baseaddr;
-
-		/* set up sector start adress table (bottom sector type)
-		 * AND unlock the sectors (if our chip is 160C3)
-		 */
-		for (i = 0; i < info->sector_count; i++) {
-			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
-			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
-				tmp[0] = 0x00600060;
-				tmp[1] = 0x00600060;
-				tmp[0] = 0x00D000D0;
-				tmp[1] = 0x00D000D0;
-			}
-			info->start[i] = (uint) tmp;
-			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
-		}
-	}
-
-	memset (info->protect, 0, info->sector_count);
-
-	baseaddr[0] = 0x00FF00FF;
-	baseaddr[1] = 0x00FF00FF;
-
-	return (info->size);
-}
-
-static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
-{
-	short i;
-	uchar vendor, devid;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0xAA;
-	addr[0x02AA] = 0x55;
-	addr[0x0555] = 0x90;
-
-	udelay(1000);
-
-	vendor = addr[0];
-	devid = addr[1] & 0xff;
-
-	/* only support AMD */
-	if (vendor != 0x01) {
-		return 0;
-	}
-
-	vendor &= 0xf;
-	devid &= 0xff;
-
-	if (devid == AMD_ID_F040B) {
-		info->flash_id     = vendor << 16 | devid;
-		info->sector_count = 8;
-		info->size         = info->sector_count * 0x10000;
-	}
-	else if (devid == AMD_ID_F080B) {
-		info->flash_id     = vendor << 16 | devid;
-		info->sector_count = 16;
-		info->size         = 4 * info->sector_count * 0x10000;
-	}
-	else if (devid == AMD_ID_F016D) {
-		info->flash_id     = vendor << 16 | devid;
-		info->sector_count = 32;
-		info->size         = 4 * info->sector_count * 0x10000;
-	}
-	else {
-		printf ("## Unknown Flash Type: %02x\n", devid);
-		return 0;
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* sector base address */
-		info->start[i] = base + i * (info->size / info->sector_count);
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned char *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (vu_char *)info->start[0];
-		addr[0] = 0xF0; /* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-	unsigned long size_b0 = 0;
-	unsigned long size_b1 = 0;
-	int i;
-
-	/* Init: no FLASHes known
-	 */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Disable flash protection */
-	CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
-
-	/* Static FLASH Bank configuration here (only one bank) */
-
-	size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-	size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
-
-	if (size_b0 > 0 || size_b1 > 0) {
-
-		printf("(");
-
-		if (size_b0 > 0) {
-			puts ("Bank#1 - ");
-			print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
-		}
-
-		if (size_b1 > 0) {
-			puts ("Bank#2 - ");
-			print_size (size_b1, ") ");
-		}
-	}
-	else {
-		printf ("## No FLASH found.\n");
-		return 0;
-	}
-	/* protect monitor and environment sectors
-	 */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
-	if (size_b1) {
-		/* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
-		 * but we shouldn't protect it.
-		 */
-
-		flash_protect  (FLAG_PROTECT_SET,
-				CONFIG_SYS_MONITOR_BASE,
-				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
-		);
-	}
-#else
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
-	);
-#endif
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
-	if (size_b1) {
-		flash_protect (FLAG_PROTECT_SET,
-				CONFIG_ENV_ADDR,
-				CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
-	}
-# else
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-# endif
-#endif
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch ((info->flash_id >> 16) & 0xff) {
-	case 0x89:
-		printf ("INTEL ");
-		break;
-	case 0x1:
-		printf ("AMD ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F160C3B:
-		printf ("28F160C3B (16 Mbit, bottom sector)\n");
-		break;
-	case FLASH_28F160F3B:
-		printf ("28F160F3B (16 Mbit, bottom sector)\n");
-		break;
-	case FLASH_28F640C3B:
-		printf ("28F640C3B (64 M, bottom sector)\n");
-		break;
-	case AMD_ID_F040B:
-		printf ("AM29F040B (4 Mbit)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	if (info->size < 0x100000)
-		printf ("  Size: %ld KB in %d Sectors\n",
-				info->size >> 10, info->sector_count);
-	else
-		printf ("  Size: %ld MB in %d Sectors\n",
-				info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	vu_char *addr = (vu_char *)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-				prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Check the type of erased flash
-	 */
-	if (info->flash_id >> 16 == 0x1) {
-		/* Erase AMD flash
-		 */
-		l_sect = -1;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr[0x0555] = 0xAA;
-		addr[0x02AA] = 0x55;
-		addr[0x0555] = 0x80;
-		addr[0x0555] = 0xAA;
-		addr[0x02AA] = 0x55;
-
-		/* wait at least 80us - let's wait 1 ms */
-		udelay (1000);
-
-		/* Start erase on unprotected sectors */
-		for (sect = s_first; sect<=s_last; sect++) {
-			if (info->protect[sect] == 0) { /* not protected */
-				addr = (vu_char *)(info->start[sect]);
-				addr[0] = 0x30;
-				l_sect = sect;
-			}
-		}
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* wait at least 80us - let's wait 1 ms */
-		udelay (1000);
-
-		/*
-		 * We wait for the last triggered sector
-		 */
-		if (l_sect < 0)
-			goto AMD_DONE;
-
-		start = get_timer (0);
-		last  = start;
-		addr = (vu_char *)(info->start[l_sect]);
-		while ((addr[0] & 0x80) != 0x80) {
-			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-				printf ("Timeout\n");
-				return 1;
-			}
-			/* show that we're waiting */
-			if ((now - last) > 1000) {      /* every second */
-				serial_putc ('.');
-				last = now;
-			}
-		}
-
-AMD_DONE:
-		/* reset to read mode */
-		addr = (volatile unsigned char *)info->start[0];
-		addr[0] = 0xF0;     /* reset bank */
-
-	} else {
-		/* Erase Intel flash
-		 */
-
-		/* Start erase on unprotected sectors
-		 */
-		for (sect = s_first; sect <= s_last; sect++) {
-			volatile ulong *addr =
-				(volatile unsigned long *) info->start[sect];
-
-			start = get_timer (0);
-			last = start;
-			if (info->protect[sect] == 0) {
-			/* Disable interrupts which might cause a timeout here
-			 */
-				flag = disable_interrupts ();
-
-				/* Erase the block
-				 */
-				addr[0] = 0x00200020;
-				addr[1] = 0x00200020;
-				addr[0] = 0x00D000D0;
-				addr[1] = 0x00D000D0;
-
-				/* re-enable interrupts if necessary
-				 */
-				if (flag)
-					enable_interrupts ();
-
-				/* wait at least 80us - let's wait 1 ms
-				 */
-				udelay (1000);
-
-				last = start;
-				while ((addr[0] & 0x00800080) != 0x00800080 ||
-				   (addr[1] & 0x00800080) != 0x00800080) {
-					if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-						printf ("Timeout (erase suspended!)\n");
-						/* Suspend erase
-						 */
-						addr[0] = 0x00B000B0;
-						addr[1] = 0x00B000B0;
-						goto DONE;
-					}
-					/* show that we're waiting
-					 */
-					if ((now - last) > 1000) {	/* every second */
-						serial_putc ('.');
-						last = now;
-					}
-				}
-				if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
-					printf ("*** ERROR: erase failed!\n");
-					goto DONE;
-				}
-			}
-			/* Clear status register and reset to read mode
-			 */
-			addr[0] = 0x00500050;
-			addr[1] = 0x00500050;
-			addr[0] = 0x00FF00FF;
-			addr[1] = 0x00FF00FF;
-		}
-	}
-
-	printf (" done\n");
-
-DONE:
-	return 0;
-}
-
-static int write_word (flash_info_t *, volatile unsigned long *, ulong);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong v;
-	int i, l, rc, cc = cnt, res = 0;
-
-	if (info->flash_id >> 16 == 0x1) {
-
-		/* Write to AMD 8-bit flash
-		 */
-		while (cnt > 0) {
-			if ((rc = write_byte(info, addr, *src)) != 0) {
-				return (rc);
-			}
-			addr++;
-			src++;
-			cnt--;
-		}
-
-		return (0);
-	} else {
-
-		/* Write to Intel 64-bit flash
-		 */
-		for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
-			l = (addr & 3);
-			addr &= ~3;
-
-			for (i = 0; i < 4; i++) {
-				v = (v << 8) + (i < l || i - l >= cc ?
-					*((unsigned char *) addr + i) : *src++);
-			}
-
-			if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
-				break;
-		}
-	}
-
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, volatile unsigned long *addr,
-					   ulong data)
-{
-	int flag, res = 0;
-	ulong start;
-
-	/* Check if Flash is (sufficiently) erased
-	 */
-	if ((*addr & data) != data)
-		return (2);
-
-	/* Disable interrupts which might cause a timeout here
-	 */
-	flag = disable_interrupts ();
-
-	*addr = 0x00400040;
-	*addr = data;
-
-	/* re-enable interrupts if necessary
-	 */
-	if (flag)
-		enable_interrupts ();
-
-	start = get_timer (0);
-	while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			/* Suspend program
-			 */
-			*addr = 0x00B000B0;
-			res = 1;
-			goto OUT;
-		}
-	}
-
-	if (*addr & 0x00220022) {
-		printf ("*** ERROR: program failed!\n");
-		res = 1;
-	}
-
-OUT:
-	/* Clear status register and reset to read mode
-	 */
-	*addr = 0x00500050;
-	*addr = 0x00FF00FF;
-
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a byte to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte (flash_info_t *info, ulong dest, uchar data)
-{
-	vu_char *addr = (vu_char *)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_char *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0xAA;
-	addr[0x02AA] = 0x55;
-	addr[0x0555] = 0xA0;
-
-	*((vu_char *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/configs/CPU86_ROMBOOT_defconfig b/configs/CPU86_ROMBOOT_defconfig
deleted file mode 100644
index 41aa7df..0000000
--- a/configs/CPU86_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_CPU86=y
diff --git a/configs/CPU86_defconfig b/configs/CPU86_defconfig
deleted file mode 100644
index f0a4049..0000000
--- a/configs/CPU86_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_CPU86=y
diff --git a/configs/CPU87_ROMBOOT_defconfig b/configs/CPU87_ROMBOOT_defconfig
deleted file mode 100644
index ba13b40..0000000
--- a/configs/CPU87_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_CPU87=y
diff --git a/configs/CPU87_defconfig b/configs/CPU87_defconfig
deleted file mode 100644
index 86a5737..0000000
--- a/configs/CPU87_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_CPU87=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 400eea1..c0d0cd9 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+CPU86            powerpc     mpc8260        -           -           Wolfgang Denk <wd@denx.de>
+CPU87            powerpc     mpc8260        -           -
 ep82xxm          powerpc     mpc8260        -           -
 gw8260           powerpc     mpc8260        -           -           Oliver Brown <obrown@adventnetworks.com>
 IPHASE4539       powerpc     mpc8260        -           -           Wolfgang Grandegger <wg@denx.de>
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
deleted file mode 100644
index 7be83b0..0000000
--- a/include/configs/CPU86.h
+++ /dev/null
@@ -1,629 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_CPU86		1	/* ...on a CPU86 board	*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#ifdef CONFIG_BOOT_ROM
-#define CONFIG_SYS_TEXT_BASE	0xFF800000
-#else
-#define	CONFIG_SYS_TEXT_BASE	0xFF000000
-#endif
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef  CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK12
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	64000000	/* in Hz */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PREBOOT								\
-	"echo; "								\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "	\
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-
-/*-----------------------------------------------------------------------
- * I2C/EEPROM/RTC configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configuration options
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash configuration
- */
-
-#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
-#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-/*-----------------------------------------------------------------------
- * Other areas to be mapped
- */
-
-/* CS3: Dual ported SRAM */
-#define CONFIG_SYS_DPSRAM_BASE		0x40000000
-#define CONFIG_SYS_DPSRAM_SIZE		0x00020000
-
-/* CS4: DiskOnChip */
-#define CONFIG_SYS_DOC_BASE		0xF4000000
-#define CONFIG_SYS_DOC_SIZE		0x00100000
-
-/* CS5: FDC37C78 controller */
-#define CONFIG_SYS_FDC37C78_BASE	0xF1000000
-#define CONFIG_SYS_FDC37C78_SIZE	0x00100000
-
-/* CS6: Board configuration registers */
-#define CONFIG_SYS_BCRS_BASE		0xF2000000
-#define CONFIG_SYS_BCRS_SIZE		0x00010000
-
-/* CS7: VME Extended Access Range */
-#define CONFIG_SYS_VMEEAR_BASE		0x80000000
-#define CONFIG_SYS_VMEEAR_SIZE		0x01000000
-
-/* CS8: VME Standard Access Range */
-#define CONFIG_SYS_VMESAR_BASE		0xFE000000
-#define CONFIG_SYS_VMESAR_SIZE		0x01000000
-
-/* CS9: VME Short I/O Access Range */
-#define CONFIG_SYS_VMESIOAR_BASE	0xFD000000
-#define CONFIG_SYS_VMESIOAR_SIZE	0x01000000
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
-				 HRCW_BPS01 | HRCW_CS10PC01)
-#else
-#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#if 0
-/* environment is in Flash */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#ifdef CONFIG_BOOT_ROM
-# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x70000)
-# define CONFIG_ENV_SIZE		0x10000
-# define CONFIG_ENV_SECT_SIZE	0x10000
-#endif
-#else
-/* environment is in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM	1
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CONFIG_ENV_OFFSET		512
-#define CONFIG_ENV_SIZE		(2048 - 512)
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
-			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define BCR_APD01	0x10000000
-#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
-			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR        SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR        0
-
-#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescaler Register              10-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MPTPR       0x1F00
-
-/*-----------------------------------------------------------------------
- * PSRT - Refresh Timer Register                                10-16
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PSRT        0x0f
-
-/*-----------------------------------------------------------------------
- * PSRT - SDRAM Mode Register                                   10-10
- *-----------------------------------------------------------------------
- */
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A9		|\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
-			 PSDMR_BSMA_A14_A16		|\
-			 PSDMR_SDA10_PBI0_A10		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_1W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A7		|\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
-			 PSDMR_BSMA_A13_A15		|\
-			 PSDMR_SDA10_PBI0_A9		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_1W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    8  bit  Boot ROM
- *  1   60x     GPCM    64 bit  FLASH
- *  2   60x     SDRAM   64 bit  SDRAM
- *
- */
-
-#define CONFIG_SYS_MRS_OFFS	0x00000000
-
-#ifdef CONFIG_BOOT_ROM
-/* Bank 0 - Boot ROM
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 1 - FLASH
- */
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-#else /* CONFIG_BOOT_ROM */
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 1 - Boot ROM
- */
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-#endif /* CONFIG_BOOT_ROM */
-
-
-/* Bank 2 - 60x bus SDRAM
- */
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_9COL
-
-#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_9COL
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/* Bank 3 - Dual Ported SRAM
- */
-#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_5_CLK                 |\
-			 ORxG_SETA)
-
-/* Bank 4 - DiskOnChip
- */
-#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
-			 ORxG_ACS_DIV2                  |\
-			 ORxG_SCY_5_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 5 - FDC37C78 controller
- */
-#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
-			 BRx_PS_8                         |\
-			 BRx_MS_GPCM_P                    |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
-			 ORxG_ACS_DIV2                    |\
-			 ORxG_SCY_8_CLK                   |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 6 - Board control registers
- */
-#define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_SCY_5_CLK)
-
-/* Bank 7 - VME Extended Access Range
- */
-#define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_32                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_5_CLK                 |\
-			 ORxG_SETA)
-
-/* Bank 8 - VME Standard Access Range
- */
-#define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_5_CLK                 |\
-			 ORxG_SETA)
-
-/* Bank 9 - VME Short I/O Access Range
- */
-#define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16                        |\
-			 BRx_MS_GPCM_P                    |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
-			 ORxG_CSNT                        |\
-			 ORxG_ACS_DIV1                    |\
-			 ORxG_SCY_5_CLK                   |\
-			 ORxG_SETA)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
deleted file mode 100644
index d3a59e8..0000000
--- a/include/configs/CPU87.h
+++ /dev/null
@@ -1,676 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_CPU87		1	/* ...on a CPU87 board	*/
-#define CONFIG_PCI
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#ifdef CONFIG_BOOT_ROM
-#define CONFIG_SYS_TEXT_BASE	0xFF800000
-#else
-#define	CONFIG_SYS_TEXT_BASE	0xFF000000
-#endif
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
-#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-
-#define	CONFIG_HAS_ETH1		1
-#define	CONFIG_HAS_ETH2		1
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK12
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	100000000	/* in Hz */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PREBOOT								\
-	"echo; "								\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "	\
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-
-/*-----------------------------------------------------------------------
- * I2C/EEPROM/RTC configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else	iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else	iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configuration options
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-    #define CONFIG_CMD_PCI
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
-
-#define CONFIG_LOOPW
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash configuration
- */
-
-#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
-#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Other areas to be mapped
- */
-
-/* CS3: Dual ported SRAM */
-#define CONFIG_SYS_DPSRAM_BASE		0x40000000
-#define CONFIG_SYS_DPSRAM_SIZE		0x00100000
-
-/* CS4: DiskOnChip */
-#define CONFIG_SYS_DOC_BASE		0xF4000000
-#define CONFIG_SYS_DOC_SIZE		0x00100000
-
-/* CS5: FDC37C78 controller */
-#define CONFIG_SYS_FDC37C78_BASE	0xF1000000
-#define CONFIG_SYS_FDC37C78_SIZE	0x00100000
-
-/* CS6: Board configuration registers */
-#define CONFIG_SYS_BCRS_BASE		0xF2000000
-#define CONFIG_SYS_BCRS_SIZE		0x00010000
-
-/* CS7: VME Extended Access Range */
-#define CONFIG_SYS_VMEEAR_BASE		0x60000000
-#define CONFIG_SYS_VMEEAR_SIZE		0x01000000
-
-/* CS8: VME Standard Access Range */
-#define CONFIG_SYS_VMESAR_BASE		0xFE000000
-#define CONFIG_SYS_VMESAR_SIZE		0x01000000
-
-/* CS9: VME Short I/O Access Range */
-#define CONFIG_SYS_VMESIOAR_BASE	0xFD000000
-#define CONFIG_SYS_VMESIOAR_SIZE	0x01000000
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
-				 HRCW_BPS01 | HRCW_CS10PC01)
-#else
-#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef	CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
-#endif
-
-#if 0
-/* environment is in Flash */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#ifdef CONFIG_BOOT_ROM
-# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x70000)
-# define CONFIG_ENV_SIZE		0x10000
-# define CONFIG_ENV_SECT_SIZE	0x10000
-#endif
-#else
-/* environment is in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM	1
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CONFIG_ENV_OFFSET		512
-#define CONFIG_ENV_SIZE		(2048 - 512)
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
-			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL	(HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR		RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define BCR_APD01	0x10000000
-#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
-			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR	SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR	0
-
-#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
-
-/*
- * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
- * refresh rate = 7.68 uS (100 MHz Bus Clock)
- */
-
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescaler Register		10-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MPTPR	0x2000
-
-/*-----------------------------------------------------------------------
- * PSRT - Refresh Timer Register				10-16
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PSRT	0x16
-
-/*-----------------------------------------------------------------------
- * PSRT - SDRAM Mode Register					10-10
- *-----------------------------------------------------------------------
- */
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A9		|\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
-			 PSDMR_BSMA_A14_A16		|\
-			 PSDMR_SDA10_PBI0_A10		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A7		|\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
-			 PSDMR_BSMA_A13_A15		|\
-			 PSDMR_SDA10_PBI0_A9		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 10-column chips
-	 */
-#define CONFIG_SYS_OR2_10COL	(CONFIG_SYS_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI1_A4		|\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_10COL	(PSDMR_PBI			|\
-			 PSDMR_SDAM_A17_IS_A5		|\
-			 PSDMR_BSMA_A13_A15		|\
-			 PSDMR_SDA10_PBI1_A6		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus	Machine PortSz	Device
- * ---- ---	------- ------	------
- *  0	60x	GPCM	8  bit	Boot ROM
- *  1	60x	GPCM	64 bit	FLASH
- *  2	60x	SDRAM	64 bit	SDRAM
- *
- */
-
-#define CONFIG_SYS_MRS_OFFS	0x00000000
-
-#ifdef CONFIG_BOOT_ROM
-/* Bank 0 - Boot ROM
- */
-#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 1 - FLASH
- */
-#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-#else /* CONFIG_BOOT_ROM */
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 1 - Boot ROM
- */
-#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-#endif /* CONFIG_BOOT_ROM */
-
-
-/* Bank 2 - 60x bus SDRAM
- */
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL
-
-#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/* Bank 3 - Dual Ported SRAM
- */
-#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_7_CLK			|\
-			 ORxG_SETA)
-
-/* Bank 4 - DiskOnChip
- */
-#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR4_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV2			|\
-			 ORxG_SCY_9_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 5 - FDC37C78 controller
- */
-#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
-			 BRx_PS_8			  |\
-			 BRx_MS_GPCM_P			  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)	  |\
-			 ORxG_ACS_DIV2			  |\
-			 ORxG_SCY_10_CLK		  |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 6 - Board control registers
- */
-#define CONFIG_SYS_BR6_PRELIM	((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR6_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_SCY_7_CLK)
-
-/* Bank 7 - VME Extended Access Range
- */
-#define CONFIG_SYS_BR7_PRELIM	((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_32			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR7_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_7_CLK			|\
-			 ORxG_SETA)
-
-/* Bank 8 - VME Standard Access Range
- */
-#define CONFIG_SYS_BR8_PRELIM	((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_OR8_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_7_CLK			|\
-			 ORxG_SETA)
-
-/* Bank 9 - VME Short I/O Access Range
- */
-#define CONFIG_SYS_BR9_PRELIM	((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16			  |\
-			 BRx_MS_GPCM_P			  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR9_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)	  |\
-			 ORxG_CSNT			  |\
-			 ORxG_ACS_DIV1			  |\
-			 ORxG_SCY_7_CLK			  |\
-			 ORxG_SETA)
-
-#endif	/* __CONFIG_H */
