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[U-Boot,v2,10/13] ARM: atmel: sama5d4: can access DDR in interleave mode

Message ID 1418621079-29668-11-git-send-email-voice.shen@atmel.com
State Accepted, archived
Delegated to: Andreas Bießmann
Headers show

Commit Message

Bo Shen Dec. 15, 2014, 5:24 a.m. UTC 
The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
---

Changes in v2: None

 arch/arm/cpu/at91-common/mpddrc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Andreas Bießmann Feb. 7, 2015, 10:46 p.m. UTC | #1 
Dear Bo Shen,

Bo Shen <voice.shen@atmel.com> writes:
>The SAMAA5D4 SoC can access DDR in interleave mode.
>
>Signed-off-by: Bo Shen <voice.shen@atmel.com>
>---
>
>Changes in v2: None
>
> arch/arm/cpu/at91-common/mpddrc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
diff mbox

Patch

diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c
index 44798e6..beec13d 100644
--- a/arch/arm/cpu/at91-common/mpddrc.c
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -19,7 +19,7 @@  static inline void atmel_mpddr_op(int mode, u32 ram_address)
 
 static int ddr2_decodtype_is_seq(u32 cr)
 {
-#if defined(CONFIG_SAMA5D3)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
 	if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
 		return 0;
 #endif