From patchwork Fri Dec 12 13:05:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 420471 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B177614003E for ; Sat, 13 Dec 2014 00:08:08 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6CFC54B96B; Fri, 12 Dec 2014 14:07:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fB8VASk5Rm7D; Fri, 12 Dec 2014 14:07:33 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7F76C4BA57; Fri, 12 Dec 2014 14:07:33 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0FB9F4BA6E for ; Fri, 12 Dec 2014 14:07:26 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id me16MF682ywO for ; Fri, 12 Dec 2014 14:07:25 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f177.google.com (mail-pd0-f177.google.com [209.85.192.177]) by theia.denx.de (Postfix) with ESMTPS id 172FD4BA1B for ; Fri, 12 Dec 2014 14:07:21 +0100 (CET) Received: by mail-pd0-f177.google.com with SMTP id ft15so7103648pdb.36 for ; Fri, 12 Dec 2014 05:07:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=j47ltHGgpWReu7fc90wQD8VWrP8wLl4CUv+u3/LlDGM=; b=EBECOX4ODLYCXLG/+jSR9WOUGUeyK1Yl1hkmechsMNq5Y3b9S+OI5HrFyPSlhjCplW IFNUoQYu8cGbKZgbae8n0ppemcioDifJAx1y4L9/8rP12yApE6P3TjpwQtdoTXrmDmEd N884sADzpQBOo66LgBgJfc+yaB4NkjuYSptiHawcL96ldrj3tmqyvJaafxMSol2A7th5 ugNawuAPXiQQ91bOYkir4gyUue13NdpIkG8l1H5JH3bdr76jd4/6Zg5b4GbDiPZDUYQb wP9NC8tzuaKFevtLsYPeP9F/mDyAziMheh7LiY92Ml3TUnIXPHd9j6/S1yJViOzYI4FL cIgQ== X-Received: by 10.66.155.2 with SMTP id vs2mr26229308pab.135.1418389640407; Fri, 12 Dec 2014 05:07:20 -0800 (PST) Received: from localhost ([106.120.101.38]) by mx.google.com with ESMTPSA id b16sm1544577pdj.76.2014.12.12.05.07.18 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 12 Dec 2014 05:07:19 -0800 (PST) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Fri, 12 Dec 2014 21:05:31 +0800 Message-Id: <1418389545-11254-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1418389545-11254-1-git-send-email-bmeng.cn@gmail.com> References: <1418389545-11254-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 13/27] x86: Support Intel FSP initialization path in start.S X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Per Intel FSP architecture specification, FSP provides 3 routines for bootloader to call. The first one is the TempRamInit (aka Cache-As-Ram initialization) and the second one is the FspInit which does the memory bring up (like MRC for other x86 targets) and chipset initialization. Those two routines have to be called before U-Boot jumping to board_init_f in start.S. The FspInit() will return several memory blocks called Hand Off Blocks (HOBs) whose format is described in Platform Initialization (PI) specification (part of the UEFI specication) to the bootloader. Save this HOB address to the U-Boot global data for later use. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v3: None Changes in v2: - Move FspInit call from start.S to car_init arch/x86/cpu/start.S | 14 ++++++++++++++ arch/x86/include/asm/global_data.h | 3 +++ arch/x86/lib/asm-offsets.c | 3 +++ 3 files changed, 20 insertions(+) diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index f9662fb..125782c 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -75,6 +75,7 @@ early_board_init_ret: jmp car_init .globl car_init_ret car_init_ret: +#ifndef CONFIG_HAVE_FSP /* * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, * or fully initialised SDRAM - we really don't care which) @@ -95,6 +96,12 @@ car_init_ret: #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp #endif +#else + /* + * When we get here after car_init, esp points to a temporary stack + * and esi holds the HOB list address returned by the FSP. + */ +#endif /* Reserve space on stack for global data */ subl $GENERATED_GBL_DATA_SIZE, %esp @@ -109,6 +116,13 @@ car_init_ret: movl %esp, %edi rep stosb +#ifdef CONFIG_HAVE_FSP + /* Store HOB list */ + movl %esp, %edx + addl $GD_HOB_LIST, %edx + movl %esi, (%edx) +#endif + /* Setup first parameter to setup_gdt, pointer to global_data */ movl %esp, %eax diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 48bbd1a..03d491a 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -47,6 +47,9 @@ struct arch_global_data { enum pei_boot_mode_t pei_boot_mode; const struct pch_gpio_map *gpio_map; /* board GPIO map */ struct memory_info meminfo; /* Memory information */ +#ifdef CONFIG_HAVE_FSP + void *hob_list; /* FSP HOB list */ +#endif }; #endif diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c index 50a488f..70ccf1b 100644 --- a/arch/x86/lib/asm-offsets.c +++ b/arch/x86/lib/asm-offsets.c @@ -18,5 +18,8 @@ int main(void) { DEFINE(GD_BIST, offsetof(gd_t, arch.bist)); +#ifdef CONFIG_HAVE_FSP + DEFINE(GD_HOB_LIST, offsetof(gd_t, arch.hob_list)); +#endif return 0; }