From patchwork Wed Dec 10 12:51:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 419639 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A43861400A0 for ; Wed, 10 Dec 2014 23:52:58 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0CE424B800; Wed, 10 Dec 2014 13:52:39 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FNoDnSgOIEn6; Wed, 10 Dec 2014 13:52:38 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 83DD74B7D8; Wed, 10 Dec 2014 13:52:38 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C701E4B7E8 for ; Wed, 10 Dec 2014 13:52:36 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id N9+O0GLHQ8vJ for ; Wed, 10 Dec 2014 13:52:36 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f171.google.com (mail-pd0-f171.google.com [209.85.192.171]) by theia.denx.de (Postfix) with ESMTPS id 2A5F64B80D for ; Wed, 10 Dec 2014 13:52:29 +0100 (CET) Received: by mail-pd0-f171.google.com with SMTP id y13so2745725pdi.30 for ; Wed, 10 Dec 2014 04:52:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=gFSzBW77v/f+ZRft5wYRKRs8LXZq/nq2iSWxwjB9VbI=; b=KQSMzDGOm2MtGp3ZJGQf5b/vuTXFGs2ZV8ZCs2lJmR9h5GB3Uskuwljn7vwkjRO9I7 l1H5ZbA4HtTI0sPnI0z6eVCG2Y9IaZ48owhvuiQVqOiV/EPtJS1IdGFAwJM0PhfpNyFe DJyBO1NGoul9esYzTLoShSfY39tnJMO7p+NVkgikhxi3bleuSgCkqZo+Jsm1NcpjDtpp WVFd5W6RzY2wbmaJRZKRtYyoEVe49+VHOdMx/poln5vbdE20KOTK91TwsIccqcs4Kt5O gRKkAd3/i63BNvdJU24eJu8qcbHHWuUXijAOahoT5DnP0fgqNE9Oxy81bbznoFoNB8u9 nckQ== X-Received: by 10.66.172.238 with SMTP id bf14mr4676848pac.20.1418215948127; Wed, 10 Dec 2014 04:52:28 -0800 (PST) Received: from localhost ([106.120.101.38]) by mx.google.com with ESMTPSA id wi15sm4270705pac.21.2014.12.10.04.52.26 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 10 Dec 2014 04:52:27 -0800 (PST) From: Bin Meng To: Jagannadha Sutradharudu Teki , U-Boot Mailing List Date: Wed, 10 Dec 2014 20:51:30 +0800 Message-Id: <1418215892-17617-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1418215892-17617-1-git-send-email-bmeng.cn@gmail.com> References: <1418215892-17617-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 7/9] sf: Update Micron flash params X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Update supported read commands for Micron flash parts per datasheet. Also update flash sector size to 4KiB as long as flash supports sector erase (20h) command. Signed-off-by: Bin Meng --- drivers/mtd/spi/sf_params.c | 46 ++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 5a3a434..034d092 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -65,29 +65,29 @@ const struct spi_flash_params spi_flash_params_table[] = { {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP}, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0}, - {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0}, - {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0}, - {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0}, - {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0}, - {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0}, - {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0}, - {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0}, - {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, - {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, - {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0}, + {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0}, + {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0}, + {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"M25PE16", 0x208015, 0x1000, 4 * 1024, 512, RD_NORM, SECT_4K}, + {"M25PX16", 0x207115, 0x1000, 4 * 1024, 512, RD_NORM | DUAL_OUTPUT_FAST, SECT_4K}, + {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, + {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, + {"M25PX64", 0x207117, 0x0, 4 * 1024, 2048, RD_NORM | DUAL_OUTPUT_FAST, SECT_4K}, + {"N25Q32", 0x20ba16, 0x0, 4 * 1024, 1024, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q32A", 0x20bb16, 0x0, 4 * 1024, 1024, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q64", 0x20ba17, 0x0, 4 * 1024, 2048, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q64A", 0x20bb17, 0x0, 4 * 1024, 2048, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q256", 0x20ba19, 0x0, 4 * 1024, 8192, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q256A", 0x20bb19, 0x0, 4 * 1024, 8192, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q512", 0x20ba20, 0x0, 4 * 1024, 16384, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q512A", 0x20bb20, 0x0, 4 * 1024, 16384, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024", 0x20ba21, 0x0, 4 * 1024, 32768, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024A", 0x20bb21, 0x0, 4 * 1024, 32768, RD_FULL, WR_QPP | E_FSR | SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ {"SST25VF040B", 0xbf258d, 0x0, 4 * 1024, 128, RD_NORM, SECT_4K | SST_WR},