From patchwork Wed Dec 10 05:25:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 419399 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BE11D1400D5 for ; Wed, 10 Dec 2014 16:25:54 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 09D954B6B0; Wed, 10 Dec 2014 06:25:53 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vRMmZaPvai5Z; Wed, 10 Dec 2014 06:25:52 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BFEEA4B692; Wed, 10 Dec 2014 06:25:51 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2ACA34B6A2 for ; Wed, 10 Dec 2014 06:25:45 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Nn9bRu9Sy06o for ; Wed, 10 Dec 2014 06:25:45 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qc0-f201.google.com (mail-qc0-f201.google.com [209.85.216.201]) by theia.denx.de (Postfix) with ESMTPS id 5CE0B4B69A for ; Wed, 10 Dec 2014 06:25:41 +0100 (CET) Received: by mail-qc0-f201.google.com with SMTP id m20so134293qcx.0 for ; Tue, 09 Dec 2014 21:25:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QDvRKWRfnAh3oWfuP5sdzhjlZIfqiCvS4cBNn2Yob2Y=; b=Texr8VNxWyF/LsE/PmwQwGHHYbgZeLKcxquvsydrSn7evzJ9BXYRGbgRVAYQeuR/qY hLL80GEUxNAdRIT4BvBOY7iH2xFOlfHHopwkxCdMJycxUQPOl16gpQwGxFI75OOQtdQ9 UjntukKlhVEMPvdVk98etjT0dFe6Yzx5wlYEk+cl9FT6Fu8QCHl8joY/17U3tRR+JBUt ZMTLZuC1Nn3WPPfR2dxpBs8C61HkMqKtQMGzamglT4QA4B+Df63wnpEo949hctIkYrk9 RD0DL5cGX/fR2OE/2KgkNJ5M0RfkltCXYSD7LSnMnqiOFaCrvwBB028mZpCU5C5V0MEf Vvuw== X-Gm-Message-State: ALoCoQkCo0pdNv5eubG4VfM06wzAPiHgiePrnsd6NdpzFpKlVzrAPZnO5oKmKtwTSdUFq8rzVkMX X-Received: by 10.236.26.5 with SMTP id b5mr2178869yha.15.1418189139906; Tue, 09 Dec 2014 21:25:39 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id t28si114347yhb.4.2014.12.09.21.25.39 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Dec 2014 21:25:39 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id i5wvWfLo.1; Tue, 09 Dec 2014 21:25:39 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 0F0FF220BBB; Tue, 9 Dec 2014 22:25:39 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Tue, 9 Dec 2014 22:25:08 -0700 Message-Id: <1418189127-27407-5-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1418189127-27407-1-git-send-email-sjg@chromium.org> References: <1418189127-27407-1-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren , Thierry Reding Subject: [U-Boot] [PATCH v4 04/23] ARM: tegra: Implement powergate support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Thierry Reding Implement the powergate API that allows various power partitions to be power up and down. Signed-off-by: Thierry Reding Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None arch/arm/cpu/tegra-common/Makefile | 1 + arch/arm/cpu/tegra-common/powergate.c | 102 +++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra/powergate.h | 38 +++++++++ arch/arm/include/asm/arch-tegra114/powergate.h | 6 ++ arch/arm/include/asm/arch-tegra124/powergate.h | 6 ++ arch/arm/include/asm/arch-tegra20/powergate.h | 6 ++ arch/arm/include/asm/arch-tegra30/powergate.h | 6 ++ 7 files changed, 165 insertions(+) create mode 100644 arch/arm/cpu/tegra-common/powergate.c create mode 100644 arch/arm/include/asm/arch-tegra/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index a18c318..c7603ee 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -13,5 +13,6 @@ obj-y += cache.o obj-y += clock.o obj-y += lowlevel_init.o obj-y += pinmux-common.o +obj-y += powergate.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA124) += vpr.o diff --git a/arch/arm/cpu/tegra-common/powergate.c b/arch/arm/cpu/tegra-common/powergate.c new file mode 100644 index 0000000..439cff3 --- /dev/null +++ b/arch/arm/cpu/tegra-common/powergate.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include +#include + +#include +#include + +#define PWRGATE_TOGGLE 0x30 +#define PWRGATE_TOGGLE_START (1 << 8) + +#define REMOVE_CLAMPING 0x34 + +#define PWRGATE_STATUS 0x38 + +static int tegra_powergate_set(enum tegra_powergate id, bool state) +{ + u32 value, mask = state ? (1 << id) : 0, old_mask; + unsigned long start, timeout = 25; + + value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); + old_mask = value & (1 << id); + + if (mask == old_mask) + return 0; + + writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE); + + start = get_timer(0); + + while (get_timer(start) < timeout) { + value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); + if ((value & (1 << id)) == mask) + return 0; + } + + return -ETIMEDOUT; +} + +static int tegra_powergate_power_on(enum tegra_powergate id) +{ + return tegra_powergate_set(id, true); +} + +int tegra_powergate_power_off(enum tegra_powergate id) +{ + return tegra_powergate_set(id, false); +} + +static int tegra_powergate_remove_clamping(enum tegra_powergate id) +{ + unsigned long value; + + /* + * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC + * partitions reversed. This was originally introduced on Tegra20 but + * has since been carried forward for backwards-compatibility. + */ + if (id == TEGRA_POWERGATE_VDEC) + value = 1 << TEGRA_POWERGATE_PCIE; + else if (id == TEGRA_POWERGATE_PCIE) + value = 1 << TEGRA_POWERGATE_VDEC; + else + value = 1 << id; + + writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING); + + return 0; +} + +int tegra_powergate_sequence_power_up(enum tegra_powergate id, + enum periph_id periph) +{ + int err; + + reset_set_enable(periph, 1); + + err = tegra_powergate_power_on(id); + if (err < 0) + return err; + + clock_enable(periph); + + udelay(10); + + err = tegra_powergate_remove_clamping(id); + if (err < 0) + return err; + + udelay(10); + + reset_set_enable(periph, 0); + + return 0; +} diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/include/asm/arch-tegra/powergate.h new file mode 100644 index 0000000..130b58b --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/powergate.h @@ -0,0 +1,38 @@ +#ifndef _TEGRA_POWERGATE_H_ +#define _TEGRA_POWERGATE_H_ + +#include + +enum tegra_powergate { + TEGRA_POWERGATE_CPU, + TEGRA_POWERGATE_3D, + TEGRA_POWERGATE_VENC, + TEGRA_POWERGATE_PCIE, + TEGRA_POWERGATE_VDEC, + TEGRA_POWERGATE_L2, + TEGRA_POWERGATE_MPE, + TEGRA_POWERGATE_HEG, + TEGRA_POWERGATE_SATA, + TEGRA_POWERGATE_CPU1, + TEGRA_POWERGATE_CPU2, + TEGRA_POWERGATE_CPU3, + TEGRA_POWERGATE_CELP, + TEGRA_POWERGATE_3D1, + TEGRA_POWERGATE_CPU0, + TEGRA_POWERGATE_C0NC, + TEGRA_POWERGATE_C1NC, + TEGRA_POWERGATE_SOR, + TEGRA_POWERGATE_DIS, + TEGRA_POWERGATE_DISB, + TEGRA_POWERGATE_XUSBA, + TEGRA_POWERGATE_XUSBB, + TEGRA_POWERGATE_XUSBC, + TEGRA_POWERGATE_VIC, + TEGRA_POWERGATE_IRAM, +}; + +int tegra_powergate_sequence_power_up(enum tegra_powergate id, + enum periph_id periph); +int tegra_powergate_power_off(enum tegra_powergate id); + +#endif diff --git a/arch/arm/include/asm/arch-tegra114/powergate.h b/arch/arm/include/asm/arch-tegra114/powergate.h new file mode 100644 index 0000000..260ea80 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA114_POWERGATE_H_ +#define _TEGRA114_POWERGATE_H_ + +#include + +#endif /* _TEGRA114_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/powergate.h b/arch/arm/include/asm/arch-tegra124/powergate.h new file mode 100644 index 0000000..8a0cfba --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA124_POWERGATE_H_ +#define _TEGRA124_POWERGATE_H_ + +#include + +#endif /* _TEGRA124_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/powergate.h b/arch/arm/include/asm/arch-tegra20/powergate.h new file mode 100644 index 0000000..439d88b --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA20_POWERGATE_H_ +#define _TEGRA20_POWERGATE_H_ + +#include + +#endif /* _TEGRA20_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/powergate.h b/arch/arm/include/asm/arch-tegra30/powergate.h new file mode 100644 index 0000000..c70e44b --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA30_POWERGATE_H_ +#define _TEGRA30_POWERGATE_H_ + +#include + +#endif /* _TEGRA30_POWERGATE_H_ */