From patchwork Wed Dec 10 05:25:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 419403 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D45811400D5 for ; Wed, 10 Dec 2014 16:26:33 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6BB044B723; Wed, 10 Dec 2014 06:26:30 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BpgZpbo15jY1; Wed, 10 Dec 2014 06:26:30 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C8AD34B6ED; Wed, 10 Dec 2014 06:26:07 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A7EB54B6A8 for ; Wed, 10 Dec 2014 06:25:50 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4pY0SqvCxnHB for ; Wed, 10 Dec 2014 06:25:50 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f74.google.com (mail-pa0-f74.google.com [209.85.220.74]) by theia.denx.de (Postfix) with ESMTPS id 534A94B6A9 for ; Wed, 10 Dec 2014 06:25:41 +0100 (CET) Received: by mail-pa0-f74.google.com with SMTP id kq14so335675pab.5 for ; Tue, 09 Dec 2014 21:25:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nhDD+i6RX1qxgYz7rtswoxUsfvB2voluOXeqm3faeGo=; b=R1GGMwv3PbjfLXtczxuHhR1YmBPI73B+d1EOj4jucWYlHD/MHLZErgpN85bEnM0qFA E+mwJIEylMintUtrStJUGKJ0omYhpEBGciUafWVTmUv9jwh60eg2Q0B9vGiDH4aAXCkm XCxYns/QUhsRH4cdaz6WpZNot7ai44xiMBSOYKY/E9dVE7sBB6Sr2aGGoHzvHhTmsLt1 WuZ/ONOxjYvrNRPZ9IbeO7nUhMaOu+aj0vDUIpfuqaFxWTVIwRM3DctS2Owfelr+BAql XePojtLXnLs87XT0yNGQwxQ0genIiF2IPxcUBFD520Jq7Qt/3pCtzMxiR8cE9KDcGCYn aEOw== X-Gm-Message-State: ALoCoQmddgGBD2IrWe3rpv7jw32fndCAouFiT+GHy3hewo7ruKqoGUYagvbFfTCfcOUlTCNn4BtH X-Received: by 10.66.65.138 with SMTP id x10mr2157364pas.6.1418189139801; Tue, 09 Dec 2014 21:25:39 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id r6si116365yhg.1.2014.12.09.21.25.39 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Dec 2014 21:25:39 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id LAxgqCTI.1; Tue, 09 Dec 2014 21:25:39 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id E68A8220A87; Tue, 9 Dec 2014 22:25:38 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Tue, 9 Dec 2014 22:25:07 -0700 Message-Id: <1418189127-27407-4-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1418189127-27407-1-git-send-email-sjg@chromium.org> References: <1418189127-27407-1-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren , Thierry Reding Subject: [U-Boot] [PATCH v4 03/23] ARM: tegra: Provide PCIEXCLK reset ID X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Thierry Reding This reset is required for PCIe and the corresponding ID therefore needs to be defined. The enumeration value for this was properly defined on some SoCs but not on others. Similarly, some contained it in the mapping of peripheral IDs to clock IDs, other didn't. This patch defines it consistently for all supported SoC generations. Acked-by: Stephen Warren Signed-off-by: Thierry Reding Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None arch/arm/cpu/tegra20-common/clock.c | 4 ++-- arch/arm/cpu/tegra30-common/clock.c | 1 + arch/arm/include/asm/arch-tegra20/clock-tables.h | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c index d55fbc8..7b9e10c 100644 --- a/arch/arm/cpu/tegra20-common/clock.c +++ b/arch/arm/cpu/tegra20-common/clock.c @@ -333,7 +333,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 0x48 */ NONE(AFI), NONE(CORESIGHT), - NONE(RESERVED74), + NONE(PCIEXCLK), NONE(AVPUCQ), NONE(RESERVED76), NONE(RESERVED77), @@ -495,7 +495,7 @@ enum periph_id clk_id_to_periph_id(int clk_id) case PERIPH_ID_RESERVED30: case PERIPH_ID_RESERVED35: case PERIPH_ID_RESERVED56: - case PERIPH_ID_RESERVED74: + case PERIPH_ID_PCIEXCLK: case PERIPH_ID_RESERVED76: case PERIPH_ID_RESERVED77: case PERIPH_ID_RESERVED78: diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c index 8e5c498..0eb0f0a 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/cpu/tegra30-common/clock.c @@ -564,6 +564,7 @@ enum periph_id clk_id_to_periph_id(int clk_id) case PERIPH_ID_RESERVED43: case PERIPH_ID_RESERVED45: case PERIPH_ID_RESERVED56: + case PERIPH_ID_PCIEXCLK: case PERIPH_ID_RESERVED76: case PERIPH_ID_RESERVED77: case PERIPH_ID_RESERVED78: diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h index a09cb01..894be08 100644 --- a/arch/arm/include/asm/arch-tegra20/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h @@ -131,7 +131,7 @@ enum periph_id { /* 72 */ PERIPH_ID_AFI, PERIPH_ID_CORESIGHT, - PERIPH_ID_RESERVED74, + PERIPH_ID_PCIEXCLK, PERIPH_ID_AVPUCQ, PERIPH_ID_RESERVED76, PERIPH_ID_RESERVED77,