From patchwork Thu Dec 4 15:04:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 417826 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DD9CA1400DD for ; Fri, 5 Dec 2014 02:05:00 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 691F64B600; Thu, 4 Dec 2014 16:04:31 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uuhFKaaHmzis; Thu, 4 Dec 2014 16:04:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E020C4B604; Thu, 4 Dec 2014 16:04:30 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BA3444B68B for ; Thu, 4 Dec 2014 16:04:24 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kgBfeUwqaPIG for ; Thu, 4 Dec 2014 16:04:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f182.google.com (mail-pd0-f182.google.com [209.85.192.182]) by theia.denx.de (Postfix) with ESMTPS id A8D3A4B600 for ; Thu, 4 Dec 2014 16:04:16 +0100 (CET) Received: by mail-pd0-f182.google.com with SMTP id r10so17738734pdi.41 for ; Thu, 04 Dec 2014 07:04:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id; bh=oWfnQ7AdNkvFYgboR4/xUC9c7t72SOpCYQM5DHnx1go=; b=Nm3ILTjA/LYPhpRVraDA2K0wcWjKaf3j2oqvOLu7eb49LO4jjuStJaoF7oYNGIvVDj d+dWsj8Fs70pXSlq6pdfj9oDsY71rLpO2cGXH9Wn9f15S/cF2w6NjQdYm9YCt96nr+Vo bcr8lHj97t3AgrKXj7xtvUQIF7R+K0TRvNJ7IYIiRxQ6ksyKAb1HMwsA26cGqjKlHPW0 1xmZA55CaushFND4tHdxIgSZooySSxEcpNVY775sPTuz7T0/ht4Fzp9fsTK6lH9LoxWR ORY/4O+09GfHCtqZkI5GZr81QYvLUw+5sFPsiurKFZfZlI/EnX0GxiVOkacuEnyL9Uh+ aGQQ== X-Received: by 10.66.119.70 with SMTP id ks6mr19544938pab.74.1417705455437; Thu, 04 Dec 2014 07:04:15 -0800 (PST) Received: from localhost ([106.120.101.38]) by mx.google.com with ESMTPSA id w5sm26369971pds.25.2014.12.04.07.04.13 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 04 Dec 2014 07:04:14 -0800 (PST) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Thu, 4 Dec 2014 23:04:10 +0800 Message-Id: <1417705450-19867-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.8.2.1 Subject: [U-Boot] [PATCH 25/25] x86: Add a README.x86 for U-Boot on x86 support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Bin Meng --- doc/README.x86 | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 doc/README.x86 diff --git a/doc/README.x86 b/doc/README.x86 new file mode 100644 index 0000000..a79f510 --- /dev/null +++ b/doc/README.x86 @@ -0,0 +1,123 @@ +# +# Copyright (C) 2014, Simon Glass +# Copyright (C) 2014, Bin Meng +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +============= + +This document describes the information about U-Boot running on x86 targets, +including supported boards, build instructions, todo list, etc. + +Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimal adjustments +on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and Intel +Crown Bay board support running U-Boot 'bare metal'. + +As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux +kernel as part of a FIT image. It also supports a compressed zImage. + +Build Instructions +------------------ +Building U-Boot as a coreboot payload is just like building U-Boot for targets +on other architectures, like below: + +$ make coreboot-x86_defconfig +$ make all + +Building rom version U-Boot (hereafter referred to as u-boot.rom) is a little +bit tricky, as generally it requires several binary blobs which are not shipped +in the U-Boot source tree. Due to this reason, the u-boot.rom build is not +turned on by default in the U-Boot source tree. Firstly, you need turn it on +by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions: + +Firstly, you need the following binary blobs: + +* descriptor.bin - Intel flash descriptor +* me.bin - Intel Management Engine +* mrc.bin - Memory Reference Code, which sets up SDRAM +* video ROM - sets up the display + +You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin. +As for the video ROM, you can get it here [2]. + +Now you can build U-Boot and obtain u-boot.rom: + +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide including initialization of the CPU, +memory controller, chipset and certain bus interfaces. + +Downalod the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Now you can build U-Boot and obtaim u-boot.rom + +$ make crownbay_defconfig +$ make menuconfig # points FSP and CMC binary path to the correct one +$ make all + +CPU Microcode +------------- +Modern CPU usually requires a special bit stream called microcode [5] to be +loaded on the processor after power up in order to function properly. U-Boot +has already integrated these as hex dumps in the source tree. + +Driver Model +------------ +x86 has been converted to use driver model for serial and GPIO. + +Device Tree +----------- +x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to +be turned on. Not every device on the board is configured via devie tree, but +more and more devices will be added as time goes by. Check out the directory +arch/x86/dts/ for these device tree source files. + +TODO List +--------- +- MTRR support (for performance) +- Audio +- Chrome OS verified boot +- SMI and ACPI support, to provide platform info and facilities to Linux + +References +---------- +[1] http://www.coreboot.org +[2] http://www.coreboot.org/~stepan/pci8086,0166.rom +[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +[4] http://www.intel.com/fsp +[5] http://en.wikipedia.org/wiki/Microcode