From patchwork Tue Dec 2 00:48:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 416678 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5BEC1140139 for ; Tue, 2 Dec 2014 11:59:58 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EA3154B893; Tue, 2 Dec 2014 01:59:42 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pcbkib28YBMJ; Tue, 2 Dec 2014 01:59:42 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F03EA4B88F; Tue, 2 Dec 2014 01:59:33 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F3C94B81C for ; Tue, 2 Dec 2014 01:59:13 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SUnEPNpGIMi7 for ; Tue, 2 Dec 2014 01:59:13 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f73.google.com (mail-pa0-f73.google.com [209.85.220.73]) by theia.denx.de (Postfix) with ESMTPS id 073B64B81B for ; Tue, 2 Dec 2014 01:59:08 +0100 (CET) Received: by mail-pa0-f73.google.com with SMTP id lj1so1523099pab.2 for ; Mon, 01 Dec 2014 16:59:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BnarmAd0rW/frprcRbq0XhtdnX7Pmad9bKeSORLWss4=; b=mq8d5Z05mJANMz5OWkP3WoYX4GVhQjKbncBp+/lSdyYrsGqq0vcaNChqDb9adTxf0O oQQhFgpnDT52tZ4QBM7rCFVIjxjHngBeeL4zn9FIHLLOixElngGOMyatugjp32qnO/vf UQviLhcNMQlcIN4XDQFlqJ/ne9tbd98LxPB6F7ylHk/kRr1CdnVO/v17ty4joHHcTTpT ZzAz0BekfC3ExqZsV60OTqrD7ODyynzxTVLlb/AuMK4rHCx8KNS20z6HlV+VkrRrfqAU 4NCXWYeeLK1cvnxPx3qMzWxg+xWV2Wcus088RMbhstgqEigfszYlb/NGP44+vmu3dFgS aqRg== X-Gm-Message-State: ALoCoQnw7XwbUXAJOZeWE5N8pSdrcsXCY0cihkET2CVwBYLnBDuFP7KrSPboY4jkuf/xA3ay3+W+ X-Received: by 10.70.89.49 with SMTP id bl17mr40408078pdb.8.1417481946958; Mon, 01 Dec 2014 16:59:06 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id n63si773922yho.5.2014.12.01.16.59.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Dec 2014 16:59:06 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id f3WwEXNZ.1; Mon, 01 Dec 2014 16:59:06 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 6B659220BC9; Mon, 1 Dec 2014 17:49:17 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 1 Dec 2014 17:48:41 -0700 Message-Id: <1417481333-30526-14-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1417481333-30526-1-git-send-email-sjg@chromium.org> References: <1417481333-30526-1-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH 13/25] tegra: clock: Add checking for invalid clock IDs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The get_pll() function can do the wrong thing if passed values that are out of range. Add checks for this and add a function which can return a 'simple' PLL. This can be defined by SoCs with their own clocks. Signed-off-by: Simon Glass --- arch/arm/cpu/tegra-common/clock.c | 30 ++++++++++++++++++++++++++---- arch/arm/include/asm/arch-tegra/clock.h | 3 +++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 11c7435..87c2950 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -80,9 +80,18 @@ static struct clk_pll *get_pll(enum clock_id clkid) (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; assert(clock_id_is_pll(clkid)); + if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) { + debug("%s: Invalid PLL\n", __func__); + return NULL; + } return &clkrst->crc_pll[clkid]; } +__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + return NULL; +} + int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, u32 *divp, u32 *cpcon, u32 *lfcon) { @@ -109,7 +118,7 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon) { struct clk_pll *pll = get_pll(clkid); - u32 data; + u32 misc_data, data; /* * We cheat by treating all PLL (except PLLU) in the same fashion. @@ -118,8 +127,7 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, * - DCCON is always 0, doesn't conflict * - M,N, P of PLLP values are ignored for PLLP */ - data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); - writel(data, &pll->pll_misc); + misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); @@ -128,7 +136,19 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, data |= divp << PLLU_VCO_FREQ_SHIFT; else data |= divp << PLL_DIVP_SHIFT; - writel(data, &pll->pll_base); + if (pll) { + writel(misc_data, &pll->pll_misc); + writel(data, &pll->pll_base); + } else { + struct clk_pll_simple *pll = clock_get_simple_pll(clkid); + + if (!pll) { + debug("%s: Uknown simple PLL %d\n", __func__, clkid); + return 0; + } + writel(misc_data, &pll->pll_misc); + writel(data, &pll->pll_base); + } /* calculate the stable time */ return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US; @@ -430,6 +450,8 @@ unsigned clock_get_rate(enum clock_id clkid) return parent_rate; pll = get_pll(clkid); + if (!pll) + return 0; base = readl(&pll->pll_base); /* Oh for bf_unpack()... */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 9d8114c..a641a16 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -265,6 +265,9 @@ void clock_early_init(void); /* Returns a pointer to the clock source register for a peripheral */ u32 *get_periph_source_reg(enum periph_id periph_id); +/* Returns a pointer to the given 'simple' PLL */ +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); + /** * Given a peripheral ID and the required source clock, this returns which * value should be programmed into the source mux for that peripheral.