From patchwork Mon Dec 1 07:05:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 416309 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9D446140169 for ; Mon, 1 Dec 2014 18:07:06 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B92D94B7FD; Mon, 1 Dec 2014 08:06:47 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kPWl35-7Vtce; Mon, 1 Dec 2014 08:06:47 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3C5E24B801; Mon, 1 Dec 2014 08:06:44 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE8714B7C4 for ; Mon, 1 Dec 2014 08:06:41 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xSRIBgsOZt6L for ; Mon, 1 Dec 2014 08:06:41 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f170.google.com (mail-pd0-f170.google.com [209.85.192.170]) by theia.denx.de (Postfix) with ESMTPS id 18A0A4B7EE for ; Mon, 1 Dec 2014 08:06:31 +0100 (CET) Received: by mail-pd0-f170.google.com with SMTP id fp1so10339845pdb.1 for ; Sun, 30 Nov 2014 23:06:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=0hNnqImEyj9su2oQ3PmKYxYVn/Cp1tqdJldvIZBTkms=; b=eRnaBoycxRb/MZZ4uwH4C4kYLpG9a7anAG3rgbuNnE14c4nsrtr1W3StfC76+SbBWu 9O9lfVM7ryMmdHWH82KSxr1mz/YImyeH/tK5wLd5aFSKM3Yf+jt3z1NAJfhjKgv3frlz vt/Q3FbUzYEd5ILX3sySxUBj5Z4+eswh8aCeXWZxjMGB+MEYq8xmOTSB3d2cCwrtiRiL 92DiiS48DNHgxzkhskoE9Dvr3b5Nv9RkDwskPkCzNzsCLG+jKu+iRnE6xMeorPmgyiTv j9N8Is66pbONa+H7DEIMcRAUI0Jxj1gxluNdNdZ4GOo0lksr8vrRoYkMsRgMg7hnIFzx h7Jg== X-Gm-Message-State: ALoCoQkagUtKVixgVXIWoBDAQdtHiWQ+FPXLb9W2XDYgiTZIz2ZhUi8l2mx3VamcWc9R9AS6AIs1 X-Received: by 10.70.2.164 with SMTP id 4mr33126610pdv.24.1417417589999; Sun, 30 Nov 2014 23:06:29 -0800 (PST) Received: from xps-iwamatsu.renesas.com (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPSA id v7sm12599237pdl.5.2014.11.30.23.06.26 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 30 Nov 2014 23:06:27 -0800 (PST) From: Nobuhiro Iwamatsu To: u-boot@lists.denx.de, Nobuhiro Iwamatsu Date: Mon, 1 Dec 2014 16:05:54 +0900 Message-Id: <1417417556-23946-5-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1417417556-23946-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> References: <1417417556-23946-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> Cc: Nobuhiro Iwamatsu , Hisashi Nakamura Subject: [U-Boot] [PATCH 5/7] arm: rmobile: koelsch: Halt clock prior to booting kernel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Before a kernel boots, GPIO, SYS-DMAC, QSPI, MSIOF and IPMMU-GP clock is halted. Signed-off-by: Hisashi Nakamura Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/koelsch.c | 43 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 5ebbfcf..8d43f36 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -61,10 +61,49 @@ int board_early_init_f(void) return 0; } +static struct mstp_ctl { + u32 s_addr; + u32 s_dis; + u32 s_ena; + u32 r_addr; + u32 r_dis; + u32 r_ena; +} mstptbl[] = { + [0] = { SMSTPCR0, 0x00640801, 0x00400000, + RMSTPCR0, 0x00640801, 0x00000000 }, + [1] = { SMSTPCR1, 0x9B6C9B5A, 0x00000000, + RMSTPCR1, 0x9B6C9B5A, 0x00000000 }, + [2] = { SMSTPCR2, 0x100D21FC, 0x00002000, + RMSTPCR2, 0x100D21FC, 0x00000000 }, + [3] = { SMSTPCR3, 0xF08CD810, 0x00000000, + RMSTPCR3, 0xF08CD810, 0x00000000 }, + [4] = { SMSTPCR4, 0x800001C4, 0x00000180, + RMSTPCR4, 0x800001C4, 0x00000000 }, + [5] = { SMSTPCR5, 0x44C00046, 0x00000000, + RMSTPCR5, 0x44C00046, 0x00000000 }, + [7] = { SMSTPCR7, 0x05BFE618, 0x00200000, + RMSTPCR7, 0x05BFE618, 0x00000000 }, + [8] = { SMSTPCR8, 0x40C0FE85, 0x00000000, + RMSTPCR8, 0x40C0FE85, 0x00000000 }, + [9] = { SMSTPCR9, 0xFF979FFF, 0x00000000, + RMSTPCR9, 0xFF979FFF, 0x00000000 }, + [10] = { SMSTPCR10, 0xFFFEFFE0, 0x00000000, + RMSTPCR10, 0xFFFEFFE0, 0x00000000 }, + [11] = { SMSTPCR11, 0x000001C0, 0x00000000, + RMSTPCR11, 0x000001C0, 0x00000000 }, +}; + void arch_preboot_os(void) { - /* Disable TMU0 */ - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + int i; + + /* Stop all module clock */ + for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { + mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_addr, + mstptbl[i].s_dis, mstptbl[i].s_ena); + mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_addr, + mstptbl[i].r_dis, mstptbl[i].r_ena); + } } /* LSI pin pull-up control */