From patchwork Fri Nov 21 16:20:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 413110 X-Patchwork-Delegate: ijc@hellion.org.uk Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0B96414017A for ; Sat, 22 Nov 2014 03:20:40 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F8A34B913; Fri, 21 Nov 2014 17:20:37 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pXRHSgw-ESon; Fri, 21 Nov 2014 17:20:37 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EC6564B902; Fri, 21 Nov 2014 17:20:36 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 00FCE4B902 for ; Fri, 21 Nov 2014 17:20:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bzDqlbQIWgCl for ; Fri, 21 Nov 2014 17:20:33 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by theia.denx.de (Postfix) with ESMTPS id 75C6E4B8F8 for ; Fri, 21 Nov 2014 17:20:29 +0100 (CET) Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id sALGKMkK004319 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Nov 2014 11:20:22 -0500 Received: from shalem.localdomain.com (vpn1-4-252.ams2.redhat.com [10.36.4.252]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id sALGKKML010410; Fri, 21 Nov 2014 11:20:21 -0500 From: Hans de Goede To: Ian Campbell Date: Fri, 21 Nov 2014 17:20:18 +0100 Message-Id: <1416586818-20696-1-git-send-email-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] sun6i: Add gmac support for sun6i boards X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Hookup the gmac found on the sun6i / A31 SoCs. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 8 +++++ arch/arm/include/asm/arch-sunxi/cpu.h | 4 +++ arch/arm/include/asm/arch-sunxi/gpio.h | 1 + board/sunxi/gmac.c | 45 +++++++++++++++++++++++++++ configs/CSQ_CS908_defconfig | 2 +- configs/Mele_M9_defconfig | 2 +- 6 files changed, 60 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 7e810bb..4bdc0de 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -204,6 +204,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #define AHB_GATE_OFFSET_MCTL 14 +#define AHB_GATE_OFFSET_GMAC 17 #define AHB_GATE_OFFSET_MMC3 11 #define AHB_GATE_OFFSET_MMC2 10 #define AHB_GATE_OFFSET_MMC1 9 @@ -230,6 +231,12 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) + #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ #define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) @@ -265,6 +272,7 @@ struct sunxi_ccm_reg { #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ /* ahb_reset0 offsets */ +#define AHB_RESET_OFFSET_GMAC 17 #define AHB_RESET_OFFSET_MCTL 14 #define AHB_RESET_OFFSET_MMC3 11 #define AHB_RESET_OFFSET_MMC2 10 diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 90e06c0..8aeed2f 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -99,9 +99,13 @@ #define SUNXI_SCR_BASE 0x01c2c400 +#ifndef CONFIG_MACH_SUN6I #define SUNXI_GPS_BASE 0x01c30000 #define SUNXI_MALI400_BASE 0x01c40000 #define SUNXI_GMAC_BASE 0x01c50000 +#else +#define SUNXI_GMAC_BASE 0x01c30000 +#endif #define SUNXI_DRAM_COM_BASE 0x01c62000 #define SUNXI_DRAM_CTL0_BASE 0x01c63000 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index c734cf0..366c0dc 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -134,6 +134,7 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_OUTPUT 1 #define SUNXI_GPA0_EMAC 2 +#define SUN6I_GPA0_GMAC 2 #define SUN7I_GPA0_GMAC 5 #define SUNXI_GPB0_TWI0 2 diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 051aca0..571bc9e 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -13,7 +13,12 @@ int sunxi_gmac_initialize(bd_t *bis) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Set up clock gating */ +#ifndef CONFIG_MACH_SUN6I setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); +#else + setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); +#endif /* Set MII clock */ #ifdef CONFIG_RGMII @@ -33,6 +38,7 @@ int sunxi_gmac_initialize(bd_t *bis) setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); #endif +#ifndef CONFIG_MACH_SUN6I /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { #ifdef CONFIG_RGMII @@ -43,9 +49,48 @@ int sunxi_gmac_initialize(bd_t *bis) sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); sunxi_gpio_set_drv(pin, 3); } +#elif defined CONFIG_RGMII + /* Configure sun6i RGMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } +#elif defined CONFIG_GMII + /* Configure sun6i GMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 2); + } +#else + /* Configure sun6i MII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); +#endif #ifdef CONFIG_RGMII return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); +#elif defined CONFIG_GMII + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII); #else return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); #endif diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index cdc0404..679fe47 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -1,5 +1,5 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" CONFIG_FDTFILE="sun6i-a31s-cs908.dtb" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index 7e50888..6f466ca 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -1,5 +1,5 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" CONFIG_FDTFILE="sun6i-a31-m9.dtb" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y