From patchwork Thu Nov 20 13:14:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ye.Li" X-Patchwork-Id: 412706 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7BE4A1400E2 for ; Fri, 21 Nov 2014 00:18:43 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6357F4B6BD; Thu, 20 Nov 2014 14:18:39 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gSyXsHaPDF7E; Thu, 20 Nov 2014 14:18:39 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 803024B6ED; Thu, 20 Nov 2014 14:18:37 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D29AD4B6B5 for ; Thu, 20 Nov 2014 14:18:28 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qtHC5wLAYogK for ; Thu, 20 Nov 2014 14:18:28 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2on0130.outbound.protection.outlook.com [207.46.100.130]) by theia.denx.de (Postfix) with ESMTPS id 33E104B6B3 for ; Thu, 20 Nov 2014 14:18:24 +0100 (CET) Received: from DM2PR03CA0034.namprd03.prod.outlook.com (10.141.96.33) by BY1PR0301MB1222.namprd03.prod.outlook.com (25.161.203.18) with Microsoft SMTP Server (TLS) id 15.1.26.15; Thu, 20 Nov 2014 13:18:20 +0000 Received: from BN1AFFO11FD019.protection.gbl (2a01:111:f400:7c10::199) by DM2PR03CA0034.outlook.office365.com (2a01:111:e400:2428::33) with Microsoft SMTP Server (TLS) id 15.1.26.15 via Frontend Transport; Thu, 20 Nov 2014 13:18:20 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD019.mail.protection.outlook.com (10.58.52.79) with Microsoft SMTP Server (TLS) id 15.1.6.13 via Frontend Transport; Thu, 20 Nov 2014 13:18:19 +0000 Received: from leyoen-ubuntu.localdomain ([10.192.185.124]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id sAKDIC5T004965; Thu, 20 Nov 2014 06:18:17 -0700 From: Ye.Li To: Date: Thu, 20 Nov 2014 21:14:12 +0800 Message-ID: <1416489255-27370-2-git-send-email-B37916@freescale.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1416489255-27370-1-git-send-email-B37916@freescale.com> References: <1416489255-27370-1-git-send-email-B37916@freescale.com> X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Ye.Li@freescale.com; X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(199003)(189002)(104016003)(76176999)(50986999)(105606002)(229853001)(19580405001)(19580395003)(6806004)(44976005)(31966008)(68736004)(85426001)(48376002)(21056001)(46102003)(50466002)(110136001)(36756003)(2351001)(97736003)(107046002)(104166001)(99396003)(106466001)(102836001)(120916001)(95666004)(84676001)(62966003)(4396001)(50226001)(92566001)(20776003)(47776003)(93916002)(64706001)(92726001)(77156002)(575784001)(89996001)(88136002)(87936001)(87286001); DIR:OUT; SFP:1102; SCL:1; SRVR:BY1PR0301MB1222; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB1222; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:; SRVR:BY1PR0301MB1222; X-Forefront-PRVS: 0401647B7F X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:; SRVR:BY1PR0301MB1222; X-OriginatorOrg: freescale.com Cc: fabio.estevam@freescale.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v7 1/4] mx6: clock: Add thermal clock enable function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Nitin Garg Add api to check and enable pll3 as required for thermal sensor driver. Signed-off-by: Ye.Li Signed-off-by: Nitin Garg --- arch/arm/cpu/armv7/mx6/clock.c | 30 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 1 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 6c9c78c..144080e 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -673,6 +673,36 @@ void hab_caam_clock_enable(unsigned char enable) } #endif +static void enable_pll3(void) +{ + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + /* make sure pll3 is enabled */ + if ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { + /* enable pll's power */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, + &anatop->usb1_pll_480_ctrl_set); + writel(0x80, &anatop->ana_misc2_clr); + /* wait for pll lock */ + while ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) + ; + /* disable bypass */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, + &anatop->usb1_pll_480_ctrl_clr); + /* enable pll output */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, + &anatop->usb1_pll_480_ctrl_set); + } +} + +void enable_thermal_clk() +{ + enable_pll3(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 3c58a0a..8e51f9b 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -66,4 +66,5 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); void enable_enet_clk(unsigned char enable); +void enable_thermal_clk(void); #endif /* __ASM_ARCH_CLOCK_H */