From patchwork Sat Nov 15 01:18:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 411074 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 012C61400B7 for ; Sat, 15 Nov 2014 12:21:01 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 82BF0A7421; Sat, 15 Nov 2014 02:20:32 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZZg5A7IxXvU6; Sat, 15 Nov 2014 02:20:32 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A51394BABE; Sat, 15 Nov 2014 02:19:57 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 797B84BA5B for ; Sat, 15 Nov 2014 02:19:11 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WummnozGu6yL for ; Sat, 15 Nov 2014 02:19:11 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qa0-f74.google.com (mail-qa0-f74.google.com [209.85.216.74]) by theia.denx.de (Postfix) with ESMTPS id 747874BA55 for ; Sat, 15 Nov 2014 02:19:05 +0100 (CET) Received: by mail-qa0-f74.google.com with SMTP id u7so1315601qaz.1 for ; Fri, 14 Nov 2014 17:19:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7Go2ZOGU9RkD8HnfWQXuXUeoliw99VoYjRthWH16z8Y=; b=eAOK0hEiHEYtQn3u5XtXzqQv8fmxVvUptBS8GbCPp0VXjUzFjxgXRIW8HHlxYXImTj 3rerDiKkWWH7p6NvXYQxPWKtKU1/T10BqDbxJm8/ti0QS2c+XA3YUswMJ7hFtdCze0QH 11il3NDG4yYE0J3O7X/mCEBtG4EEUaw0KjXfgdKImWbI60wSyXOaFyYr2A6mP2rhD7so jzuN1u2q4U+eeyj7Iw1ZbHOqol5+BJn0QuekOdvrRbhGfOTvZCOC3M1y4zJln4114Dp/ EAI9P9z2Jdq8Bc2lNVHq0RW4XCqiD2B4aHlqEsR5tMLu6xQ68LbsQo5HrPelTudIghYn 3RlA== X-Gm-Message-State: ALoCoQlDpgF57MtfXoO+YNP0gnk39FswpovCkDDY9XMoN5a67A7X6MgBzi7lR5Wpg+BQXuNJOjPu X-Received: by 10.236.231.113 with SMTP id k107mr56221594yhq.57.1416014344673; Fri, 14 Nov 2014 17:19:04 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id t24si639573yht.2.2014.11.14.17.19.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Nov 2014 17:19:04 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id FeP2os9T.2; Fri, 14 Nov 2014 17:19:04 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id D659C221027; Fri, 14 Nov 2014 18:19:03 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Fri, 14 Nov 2014 18:18:32 -0700 Message-Id: <1416014328-26324-15-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1416014328-26324-1-git-send-email-sjg@chromium.org> References: <1416014328-26324-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH v2 14/30] x86: ivybridge: Add support for BD82x6x PCH X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add basic setup for the PCH. Signed-off-by: Simon Glass --- Changes in v2: - Use pci_write_bar32() to write to BARs arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 99 +++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/pci.c | 40 +++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 14 ++++ arch/x86/include/asm/arch-ivybridge/pch.h | 13 ++++ 5 files changed, 167 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/bd82x6x.c create mode 100644 arch/x86/include/asm/arch-ivybridge/bd82x6x.h diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 721b37e..b37fb8f 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o obj-y += early_init.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c new file mode 100644 index 0000000..fab7c53 --- /dev/null +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void bd82x6x_pci_init(pci_dev_t dev) +{ + u16 reg16; + u8 reg8; + + debug("bd82x6x PCI init.\n"); + /* Enable Bus Master */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* This device has no interrupt */ + pci_write_config8(dev, INTR, 0xff); + + /* disable parity error response and SERR */ + reg16 = pci_read_config16(dev, BCTRL); + reg16 &= ~(1 << 0); + reg16 &= ~(1 << 1); + pci_write_config16(dev, BCTRL, reg16); + + /* Master Latency Count must be set to 0x04! */ + reg8 = pci_read_config8(dev, SMLT); + reg8 &= 0x07; + reg8 |= (0x04 << 3); + pci_write_config8(dev, SMLT, reg8); + + /* Will this improve throughput of bus masters? */ + pci_write_config8(dev, PCI_MIN_GNT, 0x06); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, PSTS); + /* reg16 |= 0xf900; */ + pci_write_config16(dev, PSTS, reg16); + + reg16 = pci_read_config16(dev, SECSTS); + /* reg16 |= 0xf900; */ + pci_write_config16(dev, SECSTS, reg16); +} + +#define PCI_BRIDGE_UPDATE_COMMAND +void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) +{ + uint16_t command; + + command = pci_read_config16(dev, PCI_COMMAND); + command |= PCI_COMMAND_IO; +#ifdef PCI_BRIDGE_UPDATE_COMMAND + /* + * If we write to PCI_COMMAND, on some systems this will cause the + * ROM and APICs to become invisible. + */ + debug("%x cmd <- %02x\n", dev, command); + pci_write_config16(dev, PCI_COMMAND, command); +#else + printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); +#endif +} + +void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) +{ + uint16_t ctrl; + + ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + ctrl |= PCI_COMMAND_IO; + ctrl |= PCI_BRIDGE_CTL_VGA; + debug("%x bridge ctrl <- %04x\n", dev, ctrl); + pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + + bd82x6x_pci_dev_enable_resources(dev); +} + +int bd82x6x_init_pci_devices(void) +{ + return 0; +} + +int bd82x6x_init(void) +{ + bd82x6x_pci_init(PCH_DEV); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c index c1ae658..452d1c3 100644 --- a/arch/x86/cpu/ivybridge/pci.c +++ b/arch/x86/cpu/ivybridge/pci.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) @@ -58,3 +60,41 @@ void board_pci_setup_hose(struct pci_controller *hose) hose->region_count = 3; } + +int board_pci_pre_scan(struct pci_controller *hose) +{ + pci_dev_t dev; + u16 reg16; + + bd82x6x_init(); + + reg16 = 0xff; + dev = PCH_DEV; + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + pci_write_bar32(hose, dev, 0, 0xf0000000); + + return 0; +} + +int board_pci_post_scan(struct pci_controller *hose) +{ + int ret; + + ret = bd82x6x_init_pci_devices(); + if (ret) { + printf("bd82x6x_init_pci_devices() failed: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h new file mode 100644 index 0000000..e02520c --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_BD82X6X_H +#define _ASM_ARCH_BD82X6X_H + +void bd82x6x_pci_init(pci_dev_t dev); +int bd82x6x_init_pci_devices(void); +int bd82x6x_init(void); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index c6efdb8..aa626ad 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -19,6 +19,16 @@ #define SMBUS_IO_BASE 0x0400 +/* PCI Configuration Space (D30:F0): PCI2PCI */ +#define PSTS 0x06 +#define SMLT 0x1b +#define SECSTS 0x1e +#define INTR 0x3c +#define BCTRL 0x3e +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) + #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) @@ -343,6 +353,9 @@ #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +int lpc_init(struct pci_controller *hose, pci_dev_t dev); +void lpc_enable(pci_dev_t dev); + /** * lpc_early_init() - set up LPC serial ports and other early things *