From patchwork Wed Nov 12 00:18:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 409746 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 467F6140139 for ; Wed, 12 Nov 2014 11:22:24 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A7EA04BA9D; Wed, 12 Nov 2014 01:21:54 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id f6K6Hc4W8rUW; Wed, 12 Nov 2014 01:21:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3F81F4BA53; Wed, 12 Nov 2014 01:19:56 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 259D24B984 for ; Wed, 12 Nov 2014 01:18:49 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DAkqqqBckZ46 for ; Wed, 12 Nov 2014 01:18:49 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f201.google.com (mail-ob0-f201.google.com [209.85.214.201]) by theia.denx.de (Postfix) with ESMTPS id DA76E4B9DC for ; Wed, 12 Nov 2014 01:18:41 +0100 (CET) Received: by mail-ob0-f201.google.com with SMTP id nt9so1576806obb.4 for ; Tue, 11 Nov 2014 16:18:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ARvJXIJvZLIYdben5MT4XfP18uWVgjFhuCfv+GWgW/w=; b=m9IkurGFi6J5XFNrvtDmyEJp3m9/Twi97a16jK9sFH6yrnTX4K71G5+DxDKRUaZyYj bgImmdewqcW+9Sju2VclOyJraXSokxPb7arDvTG9HjEFPPbyn9fM45n5EuyovYpC5ebS UGXSuxGDUDTYaazmcm9E7mCjZnKpSUXR+k667xlBgbMqRZgMvmZAEs/MFax11G8Te7RX NivCs8euNOlUZwQpa20BdRaAZPjGS8CyDAMFPLjbYtJz4s7lAV3+sgHfRWqosoTFk4U4 MaWLI1ghD/WKbghtRHOFKDGmxNIqMgNnyzendzXQVPMeQha+vLxtw5DoE7zgRJH+UdFI UaqQ== X-Gm-Message-State: ALoCoQlG8ay/2XPd2IKJqISzZZ5NcUCuy5c5rwrIspygOX15M34YAiQxGGHSpakXQsSfWA+pk1dX X-Received: by 10.43.169.199 with SMTP id nn7mr40637319icc.30.1415751520463; Tue, 11 Nov 2014 16:18:40 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id r6si828736yhg.1.2014.11.11.16.18.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Nov 2014 16:18:40 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id l9DEsxcf.3; Tue, 11 Nov 2014 16:18:40 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 88066221061; Tue, 11 Nov 2014 17:18:39 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Tue, 11 Nov 2014 17:18:13 -0700 Message-Id: <1415751501-23407-26-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1415751501-23407-1-git-send-email-sjg@chromium.org> References: <1415751501-23407-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH 25/33] x86: ivybridge: Set up EHCI USB X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 2 ++ arch/x86/cpu/ivybridge/usb_ehci.c | 29 +++++++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 + 4 files changed, 33 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index c6342cd..4a00757 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -17,3 +17,4 @@ obj-y += pci.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o +obj-y += usb_ehci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index b54f5c7..1fcbc28 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -102,6 +102,8 @@ int bd82x6x_init_pci_devices(void) return -EINVAL; } bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); + bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); + bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); return 0; } diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c new file mode 100644 index 0000000..291c971 --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_ehci.c @@ -0,0 +1,29 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +void bd82x6x_usb_ehci_init(pci_dev_t dev) +{ + u32 reg32; + + /* Disable Wake on Disconnect in RMH */ + reg32 = readl(RCB_REG(0x35b0)); + reg32 |= 0x22; + writel(reg32, RCB_REG(0x35b0)); + + debug("EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + /* reg32 |= PCI_COMMAND_SERR; */ + pci_write_config32(dev, PCI_COMMAND, reg32); + + debug("done.\n"); +} diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 644755f..2e6a079 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -10,6 +10,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); void bd82x6x_pci_init(pci_dev_t dev); +void bd82x6x_usb_ehci_init(pci_dev_t dev); int bd82x6x_init_pci_devices(void); int bd82x6x_init(void);