From patchwork Thu Nov 6 20:20:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 407704 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EF0BB14008C for ; Fri, 7 Nov 2014 07:25:10 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DE6974BCF9; Thu, 6 Nov 2014 21:23:44 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7Qma9oYl08or; Thu, 6 Nov 2014 21:23:44 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 96B0B4BDB8; Thu, 6 Nov 2014 21:23:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D71DC4BA66 for ; Thu, 6 Nov 2014 21:21:31 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FhVHzULtcB41 for ; Thu, 6 Nov 2014 21:21:31 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ie0-f201.google.com (mail-ie0-f201.google.com [209.85.223.201]) by theia.denx.de (Postfix) with ESMTPS id 6A6454BC0C for ; Thu, 6 Nov 2014 21:21:25 +0100 (CET) Received: by mail-ie0-f201.google.com with SMTP id rd18so561797iec.2 for ; Thu, 06 Nov 2014 12:21:23 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/bUyezP2o56Qdq3EFqOo5zosqQQAaBnxDP7e7v8neTo=; b=GbKqgK/zIcipKLtgIz0aPl96ELTZwrsQj3xnOr4AMM4vpfdRA/xzmNC0KDE+6+uioi sVvPA9dV/m2HigvgDGULShKdqcr8DyCh9Q3WGakAfi6G4xIFEOqahE5RVJWgsde+YV/r KJn+ZoV4M5V8JknkYfpZVmVabfL8xZ6mPh8i+hoqdT1bAEIpkh9aW43LIP2ShFpOaJhv WfmQSyxMzqRUrbgCxAphHTj26gXSdDHSko15IOuwQrqkfncR19MSzegMC6LeoHGKdc0+ uIcVhP28mA3yKXDIysnT4kzJpwzZd6Yq3XBVNn7wAkfnxr+vGmxQOI7S50Ju4+GFzN2S ZAKw== X-Gm-Message-State: ALoCoQnPfs8hLbG/0UJvhgMCRls4iX/pTProGHgxy1IW6gn1maLi7tApyZyYDpJdSGWjHDT4s6+T X-Received: by 10.182.98.232 with SMTP id el8mr5387109obb.42.1415305283818; Thu, 06 Nov 2014 12:21:23 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id e24si272138yhe.3.2014.11.06.12.21.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Nov 2014 12:21:23 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id Ox6wkB2d.3; Thu, 06 Nov 2014 12:21:23 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 3BC5D220169; Thu, 6 Nov 2014 13:21:23 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 6 Nov 2014 13:20:12 -0700 Message-Id: <1415305231-30180-21-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1415305231-30180-1-git-send-email-sjg@chromium.org> References: <1415305231-30180-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH 20/39] x86: Emit post codes in startup code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass --- arch/x86/cpu/coreboot/coreboot.c | 3 ++- arch/x86/cpu/start.S | 25 +++++++++++++++++++++++++ arch/x86/include/asm/post.h | 32 ++++++++++++++++++++++++++++++++ board/google/chromebook_link/Kconfig | 4 ++++ 4 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/post.h diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 257faa1..cc7398f 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -68,7 +69,7 @@ void show_boot_progress(int val) gd->arch.tsc_prev = now; } #endif - outb(val, 0x80); + outb(val, POST_PORT); } int last_stage_init(void) diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 7f41475..f62ffeb 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -60,6 +61,28 @@ _start: movw %ax, %es movw %ax, %ss + /* Enable post codes to EC */ +#ifdef CONFIG_EARLY_POST_CROS_EC + mov $0x1b, %ecx + rdmsr + and $0x100, %eax + test %eax, %eax + je 2f + + mov $0x8000f8f0, %eax + mov $0xcf8, %dx + out %eax, (%dx) + mov $0xfed1c001, %eax + mov $0xcfc, %dx + out %eax, (%dx) + mov $0xfed1f410, %esp + mov (%esp), %eax + and $0xfffffffb, %eax + mov %eax, (%esp) +2: +#endif + post_code(POST_START) + /* Clear the interrupt vectors */ lidt blank_idt_ptr @@ -91,6 +114,7 @@ car_init_ret: /* Align global data to 16-byte boundary */ andl $0xfffffff0, %esp + post_code(POST_START_STACK) /* Zero the global data since it won't happen later */ xorl %eax, %eax @@ -126,6 +150,7 @@ car_init_ret: call setup_gdt /* Set parameter to board_init_f() to boot flags */ + post_code(POST_START_DONE) xorl %eax, %eax /* Enter, U-boot! */ diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h new file mode 100644 index 0000000..3371185 --- /dev/null +++ b/arch/x86/include/asm/post.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _post_h +#define _post_h + +/* port to use for post codes */ +#define POST_PORT 0x80 + +/* post codes which represent various stages of init */ +#define POST_START 0x1e +#define POST_CAR_START 0x1f + +#define POST_START_STACK 0x29 +#define POST_START_DONE 0x2a + +/* Output a post code using al - value must be 0 to 0xff */ +#ifdef __ASSEMBLY__ +#define post_code(value) \ + movb $value, %al; \ + outb %al, $POST_PORT +#else +static inline void post_code(int code) +{ + outb(code, POST_PORT); +} +#endif + +#endif diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 975d557..9c715ba 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -12,4 +12,8 @@ config SYS_SOC config SYS_CONFIG_NAME default "chromebook_link" +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + default y + endif