From patchwork Thu Nov 6 20:20:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 407703 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6C34A14008C for ; Fri, 7 Nov 2014 07:25:02 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 98F724BB27; Thu, 6 Nov 2014 21:23:38 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BKOeW2agm0oZ; Thu, 6 Nov 2014 21:23:38 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BB5364BCFF; Thu, 6 Nov 2014 21:23:19 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 84BED4BA41 for ; Thu, 6 Nov 2014 21:21:31 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id D0Sb19IMPIlk for ; Thu, 6 Nov 2014 21:21:31 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oi0-f74.google.com (mail-oi0-f74.google.com [209.85.218.74]) by theia.denx.de (Postfix) with ESMTPS id 6A6724BC0E for ; Thu, 6 Nov 2014 21:21:25 +0100 (CET) Received: by mail-oi0-f74.google.com with SMTP id u20so259771oif.5 for ; Thu, 06 Nov 2014 12:21:23 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1Z1U1e2hWXxM/80vqeF1/MStdh1iuwGaGi2552FrD5U=; b=FGwd1s4u1NCcwtux2TyiiSkALx+ZeWJDBum9Y0kCkcqwmpzLB8VrjZY0tdRHfma+jB dmgki0p5Ve/Ph9muNbliKTIP1i4Z8Mdjc9VfSBVBe9JrTuHova18gNP5K4t5SMwzpeqi aU1KfzBr3IQwnrnwgEtwiDT/teZsJWGNjkb6hlkZVkT30yZoYuyJTCAclrKsXDopzIXW qP5sbL6jdzRG9eICwiQ5IJHc3ZugLyo09M6vUzw8Z9OhDkbrsiPeRItBvSlq6WfVIgOG 50BfamjPOgdVE6hCyfLZAVhwVJGjKyhAMawLZfHmFhT/kv/RGQ2CiaJRhCOeHgrUkCwm 6TCg== X-Gm-Message-State: ALoCoQnDCp0WVHM9vkyOf4V36mcRejhqRkx/4DlSgLPjaRt2VW5ogt8Q50TquuVUZdyR/JRYQ561 X-Received: by 10.182.245.162 with SMTP id xp2mr2220342obc.8.1415305283636; Thu, 06 Nov 2014 12:21:23 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id 5si270396yhd.6.2014.11.06.12.21.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Nov 2014 12:21:23 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id qP9gYgtF.3; Thu, 06 Nov 2014 12:21:23 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 232B4220CDC; Thu, 6 Nov 2014 13:21:23 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 6 Nov 2014 13:20:11 -0700 Message-Id: <1415305231-30180-20-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1415305231-30180-1-git-send-email-sjg@chromium.org> References: <1415305231-30180-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH 19/39] x86: Build a .rom file which can be flashed to an x86 machine X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On x86 machines U-Boot needs to be added to a large ROM image which is then flashed onto the target board. The ROM has a particular format so it makes sense for U-Boot to build this image automatically. Unfortunately it relies on binary blobs so we cannot require this for the default build as yet. Create a u-boot.rom output file for this purpose. Signed-off-by: Simon Glass --- Makefile | 27 ++++++++++++++++++++++++++- arch/x86/Kconfig | 4 ++++ include/configs/chromebook_link.h | 2 ++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9c8a580..86d0510 100644 --- a/Makefile +++ b/Makefile @@ -743,6 +743,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf +# We can't do this yet due to the need for binary blobs +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) ifeq ($(CONFIG_SPL),y) @@ -804,7 +807,8 @@ OBJCOPYFLAGS_u-boot.srec := -O srec u-boot.hex u-boot.srec: u-boot FORCE $(call if_changed,objcopy) -OBJCOPYFLAGS_u-boot.bin := -O binary +OBJCOPYFLAGS_u-boot.bin := -O binary \ + $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec) binary_size_check: u-boot.bin FORCE @file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \ @@ -943,6 +947,27 @@ u-boot-nand.gph: u-boot.bin FORCE $(call if_changed,mkimage) @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@ +# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including +# reset vector) at the top, Intel ME at the bottom, and U-Boot in the middle. +ifneq ($(CONFIG_X86_RESET_VECTOR),) +rom: u-boot.rom FORCE + +u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ + $(srctree)/board/$(BOARDDIR)/descriptor.bin + $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ + -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool -w \ + $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp + $(objtree)/tools/ifdtool -w \ + $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ + u-boot.tmp + mv u-boot.tmp $@ + +OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec +u-boot-x86-16bit.bin: u-boot FORCE + $(call if_changed,objcopy) +endif + ifneq ($(CONFIG_SUNXI),) OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 07ff149..d9ce129 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -34,6 +34,10 @@ config TARGET_CHROMEBOOK_LINK endchoice +config ROM_SIZE + hex + default 0x800000 + source "arch/x86/cpu/ivybridge/Kconfig" source "board/chromebook-x86/coreboot/Kconfig" diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 1d6f55b..5e8a747 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -18,8 +18,10 @@ #define CONFIG_SYS_CAR_ADDR 0xff7e0000 #define CONFIG_SYS_CAR_SIZE (128 * 1024) #define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_SYS_X86_START16 0xfffff800 #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 8 /*