From patchwork Sat Nov 1 08:53:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 405753 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4B23614011D for ; Sat, 1 Nov 2014 19:54:15 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9B1644BBBD; Sat, 1 Nov 2014 09:54:13 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kov8i5+dy+5o; Sat, 1 Nov 2014 09:54:13 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E86AE4BBA2; Sat, 1 Nov 2014 09:54:12 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B33CF4BBA2 for ; Sat, 1 Nov 2014 09:54:09 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CbkxFxZducmu for ; Sat, 1 Nov 2014 09:54:09 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f44.google.com (mail-pa0-f44.google.com [209.85.220.44]) by theia.denx.de (Postfix) with ESMTPS id 454ED4BBA0 for ; Sat, 1 Nov 2014 09:54:05 +0100 (CET) Received: by mail-pa0-f44.google.com with SMTP id bj1so9249809pad.3 for ; Sat, 01 Nov 2014 01:54:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id; bh=HDt4b75UQJrmFvh6IGcyn3o3aGA80UglilYyV6eER/M=; b=poCXW4nKehiDuaxQxv7Ono96olWIGZ70IaOu9JQOpDXdbC+5cB9M93qQrc0LWFLHuk JLhw8TOrhHsPVLnhaIHwClIGCCcysHJtGUHy03s51HbxmkWe0sz/d8i0I6D0QiBcScz2 bjpwqsEbN1TY+XpQhGNUy4IlXzxUPEitItLZE9S3TZJ8Hlulx43BItg2hwgBAiMphAeU 4vtKYodqfORL3UAdbb0/RTKA2RE3ketxFf37HnklYuGRVpjn5hJD8dQEQluq5BLV/cx7 lw3ycLCMLmPC4a4nWRuqJb7NS5E8qLoUQ8lFjSktw0cAu1tepdd7mnEo1eXmkwaFx3/v e/dA== X-Received: by 10.66.169.132 with SMTP id ae4mr29999187pac.87.1414832044073; Sat, 01 Nov 2014 01:54:04 -0700 (PDT) Received: from localhost ([106.120.101.38]) by mx.google.com with ESMTPSA id kl8sm3029260pdb.85.2014.11.01.01.54.02 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Sat, 01 Nov 2014 01:54:03 -0700 (PDT) From: Bin Meng To: Jagannadha Sutradharudu Teki , U-Boot Mailing List Date: Sat, 1 Nov 2014 16:53:55 +0800 Message-Id: <1414832035-13456-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.8.2.1 Subject: [U-Boot] [PATCH v2 03/12] spi: sf: Support byte program for sst spi flash X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass --- drivers/mtd/spi/sf_internal.h | 2 ++ drivers/mtd/spi/sf_ops.c | 31 +++++++++++++++++++++++++++++++ drivers/mtd/spi/sf_probe.c | 8 ++++++-- drivers/spi/ich.c | 9 +++++++-- include/spi.h | 1 + 5 files changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 5b7670c..f519060 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -107,6 +107,8 @@ enum { int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf); +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); #endif /** diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 85cf22d..3703acb 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -516,4 +516,35 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, spi_release_bus(flash->spi); return ret; } + +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf) +{ + size_t actual; + int ret; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual++) { + ret = sst_byte_write(flash, offset, buf + actual); + if (ret) { + debug("SF: sst byte program failed\n"); + break; + } + offset++; + } + + if (!ret) + ret = spi_flash_cmd_write_disable(flash); + + debug("SF: sst: program %s %zu bytes @ 0x%zx\n", + ret ? "failure" : "success", len, offset - actual); + + spi_release_bus(flash->spi); + return ret; +} #endif diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 2636426..b7ff63f 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -135,8 +135,12 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, #ifndef CONFIG_DM_SPI_FLASH flash->write = spi_flash_cmd_write_ops; #if defined(CONFIG_SPI_FLASH_SST) - if (params->flags & SST_WP) - flash->write = sst_write_wp; + if (params->flags & SST_WP) { + if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + flash->write = sst_write_bp; + else + flash->write = sst_write_wp; + } #endif flash->erase = spi_flash_cmd_erase_ops; flash->read = spi_flash_cmd_read_ops; diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index b356411..16730ec 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -141,9 +141,14 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ich->slave.max_write_size = ctlr.databytes; ich->speed = max_hz; - /* ICH 7 SPI controller only supports array read command */ - if (ctlr.ich_version == 7) + /* + * ICH 7 SPI controller only supports array read command + * and byte program command for SST flash + */ + if (ctlr.ich_version == 7) { ich->slave.op_mode_rx = SPI_OPM_RX_AS; + ich->slave.op_mode_tx = SPI_OPM_TX_BP; + } return &ich->slave; } diff --git a/include/spi.h b/include/spi.h index aa0a48e..60202ee 100644 --- a/include/spi.h +++ b/include/spi.h @@ -34,6 +34,7 @@ /* SPI TX operation modes */ #define SPI_OPM_TX_QPP (1 << 0) +#define SPI_OPM_TX_BP (1 << 1) /* SPI RX operation modes */ #define SPI_OPM_RX_AS (1 << 0)