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Fri, 31 Oct 2014 18:04:27 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NEA00ISDX2RWTN0@mmp2.samsung.com>; Fri, 31 Oct 2014 18:04:27 +0900 (KST) From: Akshay Saraswat To: u-boot@lists.denx.de Date: Fri, 31 Oct 2014 14:25:53 +0530 Message-id: <1414745754-4394-7-git-send-email-akshay.s@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1414745754-4394-1-git-send-email-akshay.s@samsung.com> References: <1414745754-4394-1-git-send-email-akshay.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsWyRsSkSndOQHCIwfRGRotTfx4zWpxddpDN YuqDc4wW37ZsY7RY/noju8XbvZ3sDmwesxsusnjsnHWX3WPBplKPs3d2MHr0bVnFGMAaxWWT kpqTWZZapG+XwJVx4ahowT/OirUTrzM2MC7k6GLk5JAQMJF4enQPK4QtJnHh3nq2LkYuDiGB pYwSXSe3AyU4wIo+bnIEqRESmM4o8ecSlD2BSaLnJj+IzSagI7F9yXd2EFtEQELiV/9VRpA5 zAKTGSUO3YJICAuES+x+1cQIYrMIqEos23OXGWQ+r4CzxP4v8hCrFCTmTLLpYmTn4BRwkVhR DLHIWWLvixZWkIESAv3sEmtXfGeCGCIg8W3yIRaITlmJTQeYIR6RlDi44gbLBEbhBYwMqxhF UwuSC4qT0ouM9YoTc4tL89L1kvNzNzECA/r0v2f9OxjvHrA+xCjAwajEw7vgeFCIEGtiWXFl 7iFGU6ANE5mlRJPzgXGTVxJvaGxmZGFqYmpsZG5ppiTOu1DqZ7CQQHpiSWp2ampBalF8UWlO avEhRiYOTqkGxmkJnNyPjRzztJqvcVyfduNky2KXWyrPL7Q0bnLaJ9zzpSp5vlu3plKh29VL WhVX2xZ9zkh4e9s0nP3wj6auCK2a6t3bZ1wX0LVSl3O1/ddvoSvsNrtxlZ3CIR5XA0WNTtuV n6IUP8081/26/33Qqwku7ouShY5NWGn8jCn4fvsSvR0nSnRZlFiKMxINtZiLihMBZOf5oWMC AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFIsWRmVeSWpSXmKPExsVy+t9jQd3ZAcEhBjdPmVqc+vOY0eLssoNs FlMfnGO0+LZlG6PF8tcb2S3e7u1kd2DzmN1wkcVj56y77B4LNpV6nL2zg9Gjb8sqxgDWqAZG m4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygE5QUyhJz SoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGReOihb846xYO/E6YwPjQo4uRg4O CQETiY+bHLsYOYFMMYkL99azgdhCAtMZJf5ccoSwJzBJ9NzkB7HZBHQkti/5zg5iiwhISPzq v8rYxcjFwSwwmVHi0C2IhLBAuMTuV02MIDaLgKrEsj13mUF28Qo4S+z/Ig+xVkFiziSbLkZ2 Dk4BF4kVxRCLnCX2vmhhncDIu4CRYRWjaGpBckFxUnquoV5xYm5xaV66XnJ+7iZGcLw8k9rB uLLB4hCjAAejEg/vguNBIUKsiWXFlbmHGCU4mJVEeEXcg0OEeFMSK6tSi/Lji0pzUosPMZoC XTSRWUo0OR8Yy3kl8YbGJuamxqaWJhYmZpZK4rwHWq0DhQTSE0tSs1NTC1KLYPqYODilGhid VFf6hE2VDd/ssIY1PGNO4pXgWsUD713XSdYZ+/OIpQoJBmQf81+xv7my8ml066rffS070u87 Lr3Q27Mycs686WxCCy6tOlDhOMHozPmF89bX7ExqyHcQODUr89HjryvO3+AtiwqQSFaUaPb6 bPkr61ig31tvdgGBU+/1GSNWL66WUU+wkFViKc5INNRiLipOBAB00bZ7rQIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Fri, 31 Oct 2014 10:45:12 +0100 Cc: Akshay Saraswat , u-boot-review@google.com Subject: [U-Boot] [PATCH v3 6/7] Exynos5: ddr3: Choose between single or double channel config X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add a 4G configuration and choose it based on the number of banks declared in config file. A board with 4 SDRAM banks declared (as per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration. Signed-off-by: Doug Anderson Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass --- Changes since v2: - Rebased this patch Changes since v1: - Rebased this patch arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 4d73b45..7c0b12a 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) + DMC_OFFSET); pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; + if (CONFIG_NR_DRAM_BANKS > 4) { + /* Need both controllers. */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2; + mem->chips_per_channel = 2; + mem->chips_to_configure = 2; + } else { + /* 2GB requires a single controller */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1; + } + /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT);