From patchwork Tue Oct 28 09:36:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 404132 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DD29E14003E for ; Tue, 28 Oct 2014 20:36:36 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3143CA741A; Tue, 28 Oct 2014 10:36:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lgJ+uw5PX1lI; Tue, 28 Oct 2014 10:36:33 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E0D30A741D; Tue, 28 Oct 2014 10:36:25 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 674BEA7405 for ; Tue, 28 Oct 2014 10:36:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id s-bIYT75RdBp for ; Tue, 28 Oct 2014 10:36:16 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mo4-p04-ob.smtp.rzone.de (mo4-p04-ob.smtp.rzone.de [81.169.146.179]) by theia.denx.de (Postfix) with ESMTPS id 46710A73EA for ; Tue, 28 Oct 2014 10:36:13 +0100 (CET) X-RZG-CLASS-ID: mo04 X-RZG-AUTH: :IW0NeWC7b/q2i6W/qstXb1SBUuFnrGohfvxEndrDXKjzPMsB3oimjD61I4fPQhgcxm53 Received: from stefan-work.domain_not_set.invalid (b9168f0d.cgn.dg-w.de [185.22.143.13]) by post.strato.de (RZmta 35.10 SBL|AUTH) with ESMTPA id 207132q9S9a9ago; Tue, 28 Oct 2014 10:36:09 +0100 (CET) From: Stefan Roese To: u-boot@lists.denx.de Date: Tue, 28 Oct 2014 10:36:06 +0100 Message-Id: <1414488968-12744-8-git-send-email-sr@denx.de> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1414488968-12744-1-git-send-email-sr@denx.de> References: <1414488968-12744-1-git-send-email-sr@denx.de> Cc: Yehuda Yitschak , Tawfik Bayouk , Eran Ben-Avi Subject: [U-Boot] [PATCH v1 7/9] arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds SPL support to the db-mv784mp-gp eval board. Signed-off-by: Stefan Roese --- arch/arm/Kconfig | 1 + board/Marvell/db-mv784mp-gp/kwbimage.cfg | 2 +- configs/db-mv784mp-gp_defconfig | 5 ++-- include/configs/db-mv784mp-gp.h | 49 ++++++++++++++++++++++++++++++++ 4 files changed, 54 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3415927..c757f30 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -143,6 +143,7 @@ config KIRKWOOD config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" + select SUPPORT_SPL config TARGET_MAXBCM bool "Support maxbcm" diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg index d7ef407..cc05792 100644 --- a/board/Marvell/db-mv784mp-gp/kwbimage.cfg +++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068 +BINARY spl/u-boot-spl.bin 0000005b 00000068 diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 7aa216c..a7f13e2 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -1,2 +1,3 @@ -CONFIG_ARM=y -CONFIG_TARGET_DB_MV784MP_GP=y +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_DB_MV784MP_GP=y diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index cb03e33..1683a15 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -11,6 +11,8 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ + #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO_LATE @@ -65,4 +67,51 @@ */ #include "mv-common.h" +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds" + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_SPD_EEPROM 0x4e + #endif /* _CONFIG_DB_MV7846MP_GP_H */