From patchwork Thu Oct 23 13:36:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 402498 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8084F140095 for ; Fri, 24 Oct 2014 00:37:16 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BB319A760F; Thu, 23 Oct 2014 15:37:10 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 45c5MN1xqqxf; Thu, 23 Oct 2014 15:37:10 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A4979A75FB; Thu, 23 Oct 2014 15:37:09 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 58E2FA75FB for ; Thu, 23 Oct 2014 15:37:08 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Inhm4ilh9KtW for ; Thu, 23 Oct 2014 15:37:08 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f175.google.com (mail-pd0-f175.google.com [209.85.192.175]) by theia.denx.de (Postfix) with ESMTPS id 1246FA7613 for ; Thu, 23 Oct 2014 15:37:02 +0200 (CEST) Received: by mail-pd0-f175.google.com with SMTP id y13so1035727pdi.20 for ; Thu, 23 Oct 2014 06:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=qcZAV3CU9XEKM3yfLRSHWcpLa7BsjBWVrMFXLduZ8+g=; b=kEeEngXm68G6dRA4w4K9DJABdQ9koKAlJabY1+P/0ixt535AZtcnWX2Kwh9adomuPx qA0gJPXS3Tk0QHtFgMP5z34ZB88tdBvhFF4EkUdbSQ0H4ORCIR5B0NWIw9b3AYGK91pS KfKlhIIsd11mE0E4VAoY+AsKg6Y5AKTsjSAAjCWCh9VMhNuGMcmY04n3LmZ5tk1MRsCf 3YSAK4cYvkGUNTiBLIV0Q6mF64f5HXr0VrKKJbiRqDxqs0BvCUfyvT7uC64fsKoCGjYt 8+70O/mcPz882YAKQPRg6F1PQLqggPhR+JcAE9fTheQu+/bENsKbLrB0tkyFqARdEZ1Y mJnw== X-Received: by 10.69.31.107 with SMTP id kl11mr4973730pbd.79.1414071420938; Thu, 23 Oct 2014 06:37:00 -0700 (PDT) Received: from localhost ([106.120.101.38]) by mx.google.com with ESMTPSA id km5sm1614880pdb.18.2014.10.23.06.36.59 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 23 Oct 2014 06:37:00 -0700 (PDT) From: Bin Meng To: Jagannadha Sutradharudu Teki , U-Boot Mailing List Date: Thu, 23 Oct 2014 21:36:55 +0800 Message-Id: <1414071415-16311-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.8.2.1 Subject: [U-Boot] [PATCH 3/5] spi: sf: Support byte program for sst spi flash X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass --- drivers/mtd/spi/sf_internal.h | 2 ++ drivers/mtd/spi/sf_ops.c | 31 +++++++++++++++++++++++++++++++ drivers/mtd/spi/sf_probe.c | 8 ++++++-- drivers/spi/ich.c | 9 +++++++-- include/spi.h | 1 + 5 files changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 19d4914..c185e04 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -77,6 +77,8 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf); +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); #endif /* Send a single-byte command to the device and read the response */ diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 85cf22d..3703acb 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -516,4 +516,35 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, spi_release_bus(flash->spi); return ret; } + +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf) +{ + size_t actual; + int ret; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual++) { + ret = sst_byte_write(flash, offset, buf + actual); + if (ret) { + debug("SF: sst byte program failed\n"); + break; + } + offset++; + } + + if (!ret) + ret = spi_flash_cmd_write_disable(flash); + + debug("SF: sst: program %s %zu bytes @ 0x%zx\n", + ret ? "failure" : "success", len, offset - actual); + + spi_release_bus(flash->spi); + return ret; +} #endif diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 4d148d1..1b48955 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -138,8 +138,12 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, /* Assign spi_flash ops */ flash->write = spi_flash_cmd_write_ops; #ifdef CONFIG_SPI_FLASH_SST - if (params->flags & SST_WP) - flash->write = sst_write_wp; + if (params->flags & SST_WP) { + if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + flash->write = sst_write_bp; + else + flash->write = sst_write_wp; + } #endif flash->erase = spi_flash_cmd_erase_ops; flash->read = spi_flash_cmd_read_ops; diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index b356411..16730ec 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -141,9 +141,14 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ich->slave.max_write_size = ctlr.databytes; ich->speed = max_hz; - /* ICH 7 SPI controller only supports array read command */ - if (ctlr.ich_version == 7) + /* + * ICH 7 SPI controller only supports array read command + * and byte program command for SST flash + */ + if (ctlr.ich_version == 7) { ich->slave.op_mode_rx = SPI_OPM_RX_AS; + ich->slave.op_mode_tx = SPI_OPM_TX_BP; + } return &ich->slave; } diff --git a/include/spi.h b/include/spi.h index ffd6647..a4d3f5f 100644 --- a/include/spi.h +++ b/include/spi.h @@ -34,6 +34,7 @@ /* SPI TX operation modes */ #define SPI_OPM_TX_QPP 1 << 0 +#define SPI_OPM_TX_BP 1 << 1 /* SPI RX operation modes */ #define SPI_OPM_RX_AS 1 << 0