From patchwork Thu Oct 23 11:06:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 402443 X-Patchwork-Delegate: hs@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0262B14009A for ; Thu, 23 Oct 2014 22:06:38 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 90625A7591; Thu, 23 Oct 2014 13:06:34 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id exj4LIAmV7jm; Thu, 23 Oct 2014 13:06:34 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0754CA757F; Thu, 23 Oct 2014 13:06:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B4521A757F for ; Thu, 23 Oct 2014 13:06:28 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cVbMcuimyZKl for ; Thu, 23 Oct 2014 13:06:28 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mo4-p05-ob.smtp.rzone.de (mo4-p05-ob.smtp.rzone.de [81.169.146.182]) by theia.denx.de (Postfix) with ESMTPS id 83F9DA74F5 for ; Thu, 23 Oct 2014 13:06:24 +0200 (CEST) X-RZG-AUTH: :IW0NeWC7b/q2i6W/qstXb1SBUuFnrGohfvxEndrDXKjzPMsB3oimjD61I4fPQhgcxm8a7w== X-RZG-CLASS-ID: mo05 Received: from stefan-work.domain_not_set.invalid (b9168f78.cgn.dg-w.de [185.22.143.120]) by post.strato.de (RZmta 35.10 AUTH) with ESMTPA id z00429q9NB6IuF3; Thu, 23 Oct 2014 13:06:18 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Thu, 23 Oct 2014 13:06:18 +0200 Message-Id: <1414062378-30776-1-git-send-email-sr@denx.de> X-Mailer: git-send-email 2.1.2 Cc: Marek Vasut , Vipin Kumar , Alexey Brodkin Subject: [U-Boot] [PATCH] i2c: designware: Convert driver to multibus/multiadapter framework X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de In preparation for the SoCFPGA support of the designware I2C driver, convert this driver to the common CONFIG_SYS_I2C framework. This patch converts all users of this driver, this is: - ST spearxxx boards - AXS101 (ARC700 platform) I couldn't test this patch on those boards. Only compile tested for all spear boards. And tested on SoCFPGA. Signed-off-by: Stefan Roese Cc: Heiko Schocher Cc: Marek Vasut Cc: Vipin Kumar Cc: Alexey Brodkin Reviewed-by: Marek Vasut Acked-by: Alexey Brodkin Tested-by: Alexey Brodkin --- arch/arm/cpu/arm926ejs/spear/cpu.c | 2 +- drivers/i2c/Makefile | 2 +- drivers/i2c/designware_i2c.c | 294 ++++++++++++++++--------------------- include/configs/axs101.h | 9 +- include/configs/spear-common.h | 4 +- include/configs/x600.h | 4 +- 6 files changed, 142 insertions(+), 173 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 3757ffb..697e094 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -38,7 +38,7 @@ int arch_cpu_init(void) #if defined(CONFIG_DW_UDC) periph1_clken |= MISC_USBDENB; #endif -#if defined(CONFIG_DW_I2C) +#if defined(CONFIG_SYS_I2C_DW) periph1_clken |= MISC_I2CENB; #endif #if defined(CONFIG_ST_SMI) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 416ea4f..b38327c 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -6,7 +6,6 @@ # obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o -obj-$(CONFIG_DW_I2C) += designware_i2c.o obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_I2C_MXS) += mxs_i2c.o obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o @@ -15,6 +14,7 @@ obj-$(CONFIG_U8500_I2C) += u8500_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o +obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index c891ebd..1a4acdd 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -6,16 +6,34 @@ */ #include +#include #include #include "designware_i2c.h" -#ifdef CONFIG_I2C_MULTI_BUS -static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX]; -static unsigned int current_bus = 0; +static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) +{ + switch (adap->hwadapnr) { +#if CONFIG_SYS_I2C_BUS_MAX >= 4 + case 3: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3; +#endif +#if CONFIG_SYS_I2C_BUS_MAX >= 3 + case 2: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2; #endif +#if CONFIG_SYS_I2C_BUS_MAX >= 2 + case 1: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1; +#endif + case 0: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE; -static struct i2c_regs *i2c_regs_p = - (struct i2c_regs *)CONFIG_SYS_I2C_BASE; + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + } + + return NULL; +} /* * set_speed - Set the i2c speed mode (standard, high, fast) @@ -23,51 +41,52 @@ static struct i2c_regs *i2c_regs_p = * * Set the i2c speed mode (standard, high, fast) */ -static void set_speed(int i2c_spd) +static void set_speed(struct i2c_adapter *adap, int i2c_spd) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int cntl; unsigned int hcnt, lcnt; unsigned int enbl; /* to set speed cltr must be disabled */ - enbl = readl(&i2c_regs_p->ic_enable); + enbl = readl(&i2c_base->ic_enable); enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); + writel(enbl, &i2c_base->ic_enable); - cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK)); + cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); switch (i2c_spd) { case IC_SPEED_MODE_MAX: cntl |= IC_CON_SPD_HS; hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; - writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt); + writel(hcnt, &i2c_base->ic_hs_scl_hcnt); lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; - writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt); + writel(lcnt, &i2c_base->ic_hs_scl_lcnt); break; case IC_SPEED_MODE_STANDARD: cntl |= IC_CON_SPD_SS; hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; - writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt); + writel(hcnt, &i2c_base->ic_ss_scl_hcnt); lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; - writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt); + writel(lcnt, &i2c_base->ic_ss_scl_lcnt); break; case IC_SPEED_MODE_FAST: default: cntl |= IC_CON_SPD_FS; hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; - writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt); + writel(hcnt, &i2c_base->ic_fs_scl_hcnt); lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; - writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt); + writel(lcnt, &i2c_base->ic_fs_scl_lcnt); break; } - writel(cntl, &i2c_regs_p->ic_con); + writel(cntl, &i2c_base->ic_con); /* Enable back i2c now speed set */ enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); + writel(enbl, &i2c_base->ic_enable); } /* @@ -76,35 +95,17 @@ static void set_speed(int i2c_spd) * * Set the i2c speed. */ -int i2c_set_bus_speed(int speed) +static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) { if (speed >= I2C_MAX_SPEED) - set_speed(IC_SPEED_MODE_MAX); + set_speed(adap, IC_SPEED_MODE_MAX); else if (speed >= I2C_FAST_SPEED) - set_speed(IC_SPEED_MODE_FAST); + set_speed(adap, IC_SPEED_MODE_FAST); else - set_speed(IC_SPEED_MODE_STANDARD); - - return 0; -} + set_speed(adap, IC_SPEED_MODE_STANDARD); -/* - * i2c_get_bus_speed - Gets the i2c speed - * - * Gets the i2c speed. - */ -int i2c_get_bus_speed(void) -{ - u32 cntl; - - cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK); - - if (cntl == IC_CON_SPD_HS) - return I2C_MAX_SPEED; - else if (cntl == IC_CON_SPD_FS) - return I2C_FAST_SPEED; - else if (cntl == IC_CON_SPD_SS) - return I2C_STANDARD_SPEED; + adap->speed = speed; return 0; } @@ -112,34 +113,32 @@ int i2c_get_bus_speed(void) /* * i2c_init - Init function * @speed: required i2c speed - * @slaveadd: slave address for the device + * @slaveaddr: slave address for the device * * Initialization function. */ -void i2c_init(int speed, int slaveadd) +static void dw_i2c_init(struct i2c_adapter *adap, int speed, + int slaveaddr) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int enbl; /* Disable i2c */ - enbl = readl(&i2c_regs_p->ic_enable); + enbl = readl(&i2c_base->ic_enable); enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); + writel(enbl, &i2c_base->ic_enable); - writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con); - writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl); - writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl); - i2c_set_bus_speed(speed); - writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask); - writel(slaveadd, &i2c_regs_p->ic_sar); + writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); + writel(IC_RX_TL, &i2c_base->ic_rx_tl); + writel(IC_TX_TL, &i2c_base->ic_tx_tl); + dw_i2c_set_bus_speed(adap, speed); + writel(IC_STOP_DET, &i2c_base->ic_intr_mask); + writel(slaveaddr, &i2c_base->ic_sar); /* Enable i2c */ - enbl = readl(&i2c_regs_p->ic_enable); + enbl = readl(&i2c_base->ic_enable); enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); - -#ifdef CONFIG_I2C_MULTI_BUS - bus_initialized[current_bus] = 1; -#endif + writel(enbl, &i2c_base->ic_enable); } /* @@ -148,21 +147,22 @@ void i2c_init(int speed, int slaveadd) * * Sets the target slave address. */ -static void i2c_setaddress(unsigned int i2c_addr) +static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int enbl; /* Disable i2c */ - enbl = readl(&i2c_regs_p->ic_enable); + enbl = readl(&i2c_base->ic_enable); enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); + writel(enbl, &i2c_base->ic_enable); - writel(i2c_addr, &i2c_regs_p->ic_tar); + writel(i2c_addr, &i2c_base->ic_tar); /* Enable i2c */ - enbl = readl(&i2c_regs_p->ic_enable); + enbl = readl(&i2c_base->ic_enable); enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); + writel(enbl, &i2c_base->ic_enable); } /* @@ -170,10 +170,12 @@ static void i2c_setaddress(unsigned int i2c_addr) * * Flushes the i2c RX FIFO */ -static void i2c_flush_rxfifo(void) +static void i2c_flush_rxfifo(struct i2c_adapter *adap) { - while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) - readl(&i2c_regs_p->ic_cmd_data); + struct i2c_regs *i2c_base = i2c_get_base(adap); + + while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) + readl(&i2c_base->ic_cmd_data); } /* @@ -181,12 +183,13 @@ static void i2c_flush_rxfifo(void) * * Waits for bus busy */ -static int i2c_wait_for_bb(void) +static int i2c_wait_for_bb(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned long start_time_bb = get_timer(0); - while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) || - !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) { + while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) || + !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) { /* Evaluate timeout */ if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) @@ -196,40 +199,44 @@ static int i2c_wait_for_bb(void) return 0; } -static int i2c_xfer_init(uchar chip, uint addr, int alen) +static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr, + int alen) { - if (i2c_wait_for_bb()) + struct i2c_regs *i2c_base = i2c_get_base(adap); + + if (i2c_wait_for_bb(adap)) return 1; - i2c_setaddress(chip); + i2c_setaddress(adap, chip); while (alen) { alen--; /* high byte address going out first */ writel((addr >> (alen * 8)) & 0xff, - &i2c_regs_p->ic_cmd_data); + &i2c_base->ic_cmd_data); } return 0; } -static int i2c_xfer_finish(void) +static int i2c_xfer_finish(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = i2c_get_base(adap); ulong start_stop_det = get_timer(0); while (1) { - if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) { - readl(&i2c_regs_p->ic_clr_stop_det); + if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) { + readl(&i2c_base->ic_clr_stop_det); break; } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { break; } } - if (i2c_wait_for_bb()) { + if (i2c_wait_for_bb(adap)) { printf("Timed out waiting for bus\n"); return 1; } - i2c_flush_rxfifo(); + i2c_flush_rxfifo(adap); return 0; } @@ -244,8 +251,10 @@ static int i2c_xfer_finish(void) * * Read from i2c memory. */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *buffer, int len) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned long start_time_rx; #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW @@ -260,25 +269,25 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * still be one byte because the extra address bits are * hidden in the chip address. */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); - debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, + debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, addr); #endif - if (i2c_xfer_init(chip, addr, alen)) + if (i2c_xfer_init(adap, dev, addr, alen)) return 1; start_time_rx = get_timer(0); while (len) { if (len == 1) - writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data); + writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); else - writel(IC_CMD, &i2c_regs_p->ic_cmd_data); + writel(IC_CMD, &i2c_base->ic_cmd_data); - if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) { - *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data); + if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) { + *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data); len--; start_time_rx = get_timer(0); @@ -287,7 +296,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } } - return i2c_xfer_finish(); + return i2c_xfer_finish(adap); } /* @@ -300,8 +309,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * * Write to i2c memory. */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *buffer, int len) { + struct i2c_regs *i2c_base = i2c_get_base(adap); int nb = len; unsigned long start_time_tx; @@ -317,23 +328,25 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) * still be one byte because the extra address bits are * hidden in the chip address. */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); - debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, + debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, addr); #endif - if (i2c_xfer_init(chip, addr, alen)) + if (i2c_xfer_init(adap, dev, addr, alen)) return 1; start_time_tx = get_timer(0); while (len) { - if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) { - if (--len == 0) - writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data); - else - writel(*buffer, &i2c_regs_p->ic_cmd_data); + if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) { + if (--len == 0) { + writel(*buffer | IC_STOP, + &i2c_base->ic_cmd_data); + } else { + writel(*buffer, &i2c_base->ic_cmd_data); + } buffer++; start_time_tx = get_timer(0); @@ -343,13 +356,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } } - return i2c_xfer_finish(); + return i2c_xfer_finish(adap); } /* * i2c_probe - Probe the i2c chip */ -int i2c_probe(uchar chip) +static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev) { u32 tmp; int ret; @@ -357,80 +370,33 @@ int i2c_probe(uchar chip) /* * Try to read the first location of the chip. */ - ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1); if (ret) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + dw_i2c_init(adap, adap->speed, adap->slaveaddr); return ret; } -#ifdef CONFIG_I2C_MULTI_BUS -int i2c_set_bus_num(unsigned int bus) -{ - switch (bus) { - case 0: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE; - break; -#ifdef CONFIG_SYS_I2C_BASE1 - case 1: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE2 - case 2: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE3 - case 3: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE4 - case 4: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE5 - case 5: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE6 - case 6: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE7 - case 7: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE8 - case 8: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE9 - case 9: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9; - break; +U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read, + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) + +#if CONFIG_SYS_I2C_BUS_MAX >= 2 +U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read, + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1) #endif - default: - printf("Bad bus: %d\n", bus); - return -1; - } - current_bus = bus; - if (!bus_initialized[current_bus]) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#if CONFIG_SYS_I2C_BUS_MAX >= 3 +U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read, + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2) +#endif - return 0; -} -int i2c_get_bus_num(void) -{ - return current_bus; -} +#if CONFIG_SYS_I2C_BUS_MAX >= 4 +U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) #endif diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 1bf8390..6e8c56c 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -83,12 +83,15 @@ /* * I2C configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DW_I2C -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW #define CONFIG_I2C_ENV_EEPROM_BUS 2 #define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SPEED1 100000 +#define CONFIG_SYS_I2C_SPEED2 100000 #define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_SLAVE1 0 +#define CONFIG_SYS_I2C_SLAVE2 0 #define CONFIG_SYS_I2C_BASE 0xE001D000 #define CONFIG_SYS_I2C_BASE1 0xE001E000 #define CONFIG_SYS_I2C_BASE2 0xE001F000 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index c0eba37..a11f4ed 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -37,8 +37,8 @@ #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" /* I2C driver configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW #if defined(CONFIG_SPEAR600) #define CONFIG_SYS_I2C_BASE 0xD0200000 #elif defined(CONFIG_SPEAR300) diff --git a/include/configs/x600.h b/include/configs/x600.h index 71373e9..d39a0f8 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -83,8 +83,8 @@ #define CONFIG_SPEAR_GPIO /* I2C config options */ -#define CONFIG_HARD_I2C -#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW #define CONFIG_SYS_I2C_BASE 0xD0200000 #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02