From patchwork Tue Oct 21 01:48:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 401299 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CAA66140077 for ; Tue, 21 Oct 2014 12:50:25 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 61866A7408; Tue, 21 Oct 2014 03:50:02 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MFN5rTEzjvlb; Tue, 21 Oct 2014 03:50:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D7955A743F; Tue, 21 Oct 2014 03:49:48 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AA61EA73FA for ; Tue, 21 Oct 2014 03:49:10 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SLr+Pzeq7qpW for ; Tue, 21 Oct 2014 03:49:10 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oi0-f74.google.com (mail-oi0-f74.google.com [209.85.218.74]) by theia.denx.de (Postfix) with ESMTPS id 185C8A73FE for ; Tue, 21 Oct 2014 03:49:04 +0200 (CEST) Received: by mail-oi0-f74.google.com with SMTP id v63so41783oia.1 for ; Mon, 20 Oct 2014 18:49:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7ZqZGGt0D2BHkgHYJeOexOBtEDa0djituAKd7uPSH6g=; b=GLBKM1io3JfpBMM6DkKnCGMUu/EHr2k67fpoKe9p1O9YEVStb+gt42Y/BLv1n6W9qb 1qagkXC4wasbZuHcmmn6Is7FurlJ4YjBJ0+83ZkdET7NG6azmn/gFFgucWdqIvrxnyuj /q17yOa3hi1fjFdEsLL0Y4CIHWTGMOsrqc5duxeIUkhDViJBIDL0Mt9sni+ReSufGyrb z7VfTNTwxmp2O9+5qe3nAqhRqG9W5Ybteq/cEcwgYcGbHn5UaevR/PC/TGCJU0eZD+ca JnEIGZbk7RA2mEVVzSMy1LZqlpxmmoqUtcVVyu+akgvVvYq6OpCtrpmHPwuiO6icEbz+ 91Vg== X-Gm-Message-State: ALoCoQkiAlqgLe5Xdzo9lBJSqvWmSjbZUGvsKnikqbYVgo/EffISXQmARvaBoLo4WP6O+RiYd/Pz X-Received: by 10.182.168.114 with SMTP id zv18mr20442414obb.23.1413856143750; Mon, 20 Oct 2014 18:49:03 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id n24si482271yha.6.2014.10.20.18.49.02 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Oct 2014 18:49:03 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id jBBcc2Qu.1; Mon, 20 Oct 2014 18:49:03 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 127192214CF; Mon, 20 Oct 2014 19:49:01 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Mon, 20 Oct 2014 19:48:34 -0600 Message-Id: <1413856120-32039-7-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1413856120-32039-1-git-send-email-sjg@chromium.org> References: <1413856120-32039-1-git-send-email-sjg@chromium.org> Cc: u-boot-review@google.com, Przemyslaw Marczak , Tom Warren Subject: [U-Boot] [PATCH v10 06/12] dm: exynos: Add pinctrl settings for s5p_goni X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: Simon Glass --- Changes in v10: None Changes in v9: - Change compatible string to s5pc110-pinctrl for s5p_goni Changes in v8: - Add patch containing pinctrl settings for s5p_goni Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None arch/arm/dts/s5pc110-pinctrl.dtsi | 273 ++++++++++++++++++++++++++++++++++++++ arch/arm/dts/s5pc1xx-goni.dts | 7 + 2 files changed, 280 insertions(+) create mode 100644 arch/arm/dts/s5pc110-pinctrl.dtsi diff --git a/arch/arm/dts/s5pc110-pinctrl.dtsi b/arch/arm/dts/s5pc110-pinctrl.dtsi new file mode 100644 index 0000000..d21b6ab --- /dev/null +++ b/arch/arm/dts/s5pc110-pinctrl.dtsi @@ -0,0 +1,273 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/ { + pinctrl@e0200000 { + #address-cells = <1>; + #size-cells = <0>; + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpi: gpi { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj3: gpj3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp01: gpmp01 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp02: gpmp02 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp03: gpmp03 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp04: gpmp04 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp05: gpmp05 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp06: gpmp06 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp07: gpmp07 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp10: gpmp10 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp11: gpmp11 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp12: gpmp12 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp13: gpmp13 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp14: gpmp14 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp15: gpmp15 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp16: gpmp16 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp17: gpmp17 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp18: gpmp18 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp20: gpmp20 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp21: gpmp21 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp22: gpmp22 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp23: gpmp23 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp24: gpmp24 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp25: gpmp25 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp26: gpmp26 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp27: gpmp27 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp28: gpmp28 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph0: gph0 { + reg = <0xc00>; + gpio-controller; + #gpio-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph2: gph2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph3: gph3 { + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts index 2e671bb..7bbfe59 100644 --- a/arch/arm/dts/s5pc1xx-goni.dts +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "skeleton.dtsi" +#include "s5pc110-pinctrl.dtsi" / { model = "Samsung Goni based on S5PC110"; @@ -17,6 +18,12 @@ aliases { serial2 = "/serial@e2900800"; console = "/serial@e2900800"; + pinctrl0 = &pinctrl0; + }; + + pinctrl0: pinctrl@e0200000 { + compatible = "samsung,s5pc110-pinctrl"; + reg = <0xe0200000 0x1000>; }; serial@e2900800 {