diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index ba169b9..ad2ece6 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -284,7 +284,7 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_Y65,
 	EXYNOS4_GPIO_Y66,
 	EXYNOS4_GPIO_Y67,
-	EXYNOS4_GPIO_X00 = 896,		/* 896 0x380 */
+	EXYNOS4_GPIO_X00,		/* 256 0x100 */
 	EXYNOS4_GPIO_X01,
 	EXYNOS4_GPIO_X02,
 	EXYNOS4_GPIO_X03,
@@ -292,7 +292,7 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_X05,
 	EXYNOS4_GPIO_X06,
 	EXYNOS4_GPIO_X07,
-	EXYNOS4_GPIO_X10,		/* 904 0x388 */
+	EXYNOS4_GPIO_X10,		/* 264 0x108 */
 	EXYNOS4_GPIO_X11,
 	EXYNOS4_GPIO_X12,
 	EXYNOS4_GPIO_X13,
@@ -300,7 +300,7 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_X15,
 	EXYNOS4_GPIO_X16,
 	EXYNOS4_GPIO_X17,
-	EXYNOS4_GPIO_X20,		/* 912 0x390 */
+	EXYNOS4_GPIO_X20,		/* 272 0x110 */
 	EXYNOS4_GPIO_X21,
 	EXYNOS4_GPIO_X22,
 	EXYNOS4_GPIO_X23,
@@ -308,7 +308,7 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_X25,
 	EXYNOS4_GPIO_X26,
 	EXYNOS4_GPIO_X27,
-	EXYNOS4_GPIO_X30,		/* 920 0x398 */
+	EXYNOS4_GPIO_X30,		/* 280 0x118 */
 	EXYNOS4_GPIO_X31,
 	EXYNOS4_GPIO_X32,
 	EXYNOS4_GPIO_X33,
@@ -318,7 +318,7 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_X37,
 
 	/* GPIO_PART3_STARTS */
-	EXYNOS4_GPIO_MAX_PORT_PART_2,	/* 928 0x3A0 */
+	EXYNOS4_GPIO_MAX_PORT_PART_2,	/* 288 0x120 */
 	EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
 	EXYNOS4_GPIO_Z1,
 	EXYNOS4_GPIO_Z2,
@@ -389,7 +389,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_D15,
 	EXYNOS4X12_GPIO_D16,
 	EXYNOS4X12_GPIO_D17,
-	EXYNOS4X12_GPIO_F00 = 96,	/* 96 0x60 */
+	EXYNOS4X12_GPIO_F00,		/* 56 0x38 */
 	EXYNOS4X12_GPIO_F01,
 	EXYNOS4X12_GPIO_F02,
 	EXYNOS4X12_GPIO_F03,
@@ -397,7 +397,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_F05,
 	EXYNOS4X12_GPIO_F06,
 	EXYNOS4X12_GPIO_F07,
-	EXYNOS4X12_GPIO_F10,		/* 104 0x68 */
+	EXYNOS4X12_GPIO_F10,		/* 64 0x40 */
 	EXYNOS4X12_GPIO_F11,
 	EXYNOS4X12_GPIO_F12,
 	EXYNOS4X12_GPIO_F13,
@@ -405,7 +405,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_F15,
 	EXYNOS4X12_GPIO_F16,
 	EXYNOS4X12_GPIO_F17,
-	EXYNOS4X12_GPIO_F20,		/* 112 0x70 */
+	EXYNOS4X12_GPIO_F20,		/* 72 0x48 */
 	EXYNOS4X12_GPIO_F21,
 	EXYNOS4X12_GPIO_F22,
 	EXYNOS4X12_GPIO_F23,
@@ -413,7 +413,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_F25,
 	EXYNOS4X12_GPIO_F26,
 	EXYNOS4X12_GPIO_F27,
-	EXYNOS4X12_GPIO_F30,		/* 120 0x78 */
+	EXYNOS4X12_GPIO_F30,		/* 80 0x50 */
 	EXYNOS4X12_GPIO_F31,
 	EXYNOS4X12_GPIO_F32,
 	EXYNOS4X12_GPIO_F33,
@@ -421,7 +421,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_F35,
 	EXYNOS4X12_GPIO_F36,
 	EXYNOS4X12_GPIO_F37,
-	EXYNOS4X12_GPIO_J00 = 144,	/* 144 0x90 */
+	EXYNOS4X12_GPIO_J00,		/* 88 0x58 */
 	EXYNOS4X12_GPIO_J01,
 	EXYNOS4X12_GPIO_J02,
 	EXYNOS4X12_GPIO_J03,
@@ -429,7 +429,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_J05,
 	EXYNOS4X12_GPIO_J06,
 	EXYNOS4X12_GPIO_J07,
-	EXYNOS4X12_GPIO_J10,		/* 152 0x98 */
+	EXYNOS4X12_GPIO_J10,		/* 96 0x60 */
 	EXYNOS4X12_GPIO_J11,
 	EXYNOS4X12_GPIO_J12,
 	EXYNOS4X12_GPIO_J13,
@@ -439,8 +439,8 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_J17,
 
 	/* GPIO_PART2_STARTS */
-	EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */
-	EXYNOS4X12_GPIO_K00 = 176,	/* 176 0xB0 */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
+	EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
 	EXYNOS4X12_GPIO_K01,
 	EXYNOS4X12_GPIO_K02,
 	EXYNOS4X12_GPIO_K03,
@@ -448,7 +448,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_K05,
 	EXYNOS4X12_GPIO_K06,
 	EXYNOS4X12_GPIO_K07,
-	EXYNOS4X12_GPIO_K10,		/* 184 0xB8 */
+	EXYNOS4X12_GPIO_K10,		/* 112 0x70 */
 	EXYNOS4X12_GPIO_K11,
 	EXYNOS4X12_GPIO_K12,
 	EXYNOS4X12_GPIO_K13,
@@ -456,7 +456,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_K15,
 	EXYNOS4X12_GPIO_K16,
 	EXYNOS4X12_GPIO_K17,
-	EXYNOS4X12_GPIO_K20,		/* 192 0xC0 */
+	EXYNOS4X12_GPIO_K20,		/* 120 0x78 */
 	EXYNOS4X12_GPIO_K21,
 	EXYNOS4X12_GPIO_K22,
 	EXYNOS4X12_GPIO_K23,
@@ -464,7 +464,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_K25,
 	EXYNOS4X12_GPIO_K26,
 	EXYNOS4X12_GPIO_K27,
-	EXYNOS4X12_GPIO_K30,		/* 200 0xC8 */
+	EXYNOS4X12_GPIO_K30,		/* 128 0x80 */
 	EXYNOS4X12_GPIO_K31,
 	EXYNOS4X12_GPIO_K32,
 	EXYNOS4X12_GPIO_K33,
@@ -472,7 +472,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_K35,
 	EXYNOS4X12_GPIO_K36,
 	EXYNOS4X12_GPIO_K37,
-	EXYNOS4X12_GPIO_L00,		/* 208 0xD0 */
+	EXYNOS4X12_GPIO_L00,		/* 136 0x88 */
 	EXYNOS4X12_GPIO_L01,
 	EXYNOS4X12_GPIO_L02,
 	EXYNOS4X12_GPIO_L03,
@@ -480,7 +480,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_L05,
 	EXYNOS4X12_GPIO_L06,
 	EXYNOS4X12_GPIO_L07,
-	EXYNOS4X12_GPIO_L10,		/* 216 0xD8 */
+	EXYNOS4X12_GPIO_L10,		/* 144 0x90 */
 	EXYNOS4X12_GPIO_L11,
 	EXYNOS4X12_GPIO_L12,
 	EXYNOS4X12_GPIO_L13,
@@ -488,7 +488,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_L15,
 	EXYNOS4X12_GPIO_L16,
 	EXYNOS4X12_GPIO_L17,
-	EXYNOS4X12_GPIO_L20,		/* 224 0xE0 */
+	EXYNOS4X12_GPIO_L20,		/* 152 0x98 */
 	EXYNOS4X12_GPIO_L21,
 	EXYNOS4X12_GPIO_L22,
 	EXYNOS4X12_GPIO_L23,
@@ -496,7 +496,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_L25,
 	EXYNOS4X12_GPIO_L26,
 	EXYNOS4X12_GPIO_L27,
-	EXYNOS4X12_GPIO_Y00,		/* 232 0xE8 */
+	EXYNOS4X12_GPIO_Y00,		/* 160 0xa0 */
 	EXYNOS4X12_GPIO_Y01,
 	EXYNOS4X12_GPIO_Y02,
 	EXYNOS4X12_GPIO_Y03,
@@ -504,7 +504,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y05,
 	EXYNOS4X12_GPIO_Y06,
 	EXYNOS4X12_GPIO_Y07,
-	EXYNOS4X12_GPIO_Y10,		/* 240 0xF0 */
+	EXYNOS4X12_GPIO_Y10,		/* 168 0xa8 */
 	EXYNOS4X12_GPIO_Y11,
 	EXYNOS4X12_GPIO_Y12,
 	EXYNOS4X12_GPIO_Y13,
@@ -512,7 +512,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y15,
 	EXYNOS4X12_GPIO_Y16,
 	EXYNOS4X12_GPIO_Y17,
-	EXYNOS4X12_GPIO_Y20,		/* 248 0xF8 */
+	EXYNOS4X12_GPIO_Y20,		/* 176 0xb0 */
 	EXYNOS4X12_GPIO_Y21,
 	EXYNOS4X12_GPIO_Y22,
 	EXYNOS4X12_GPIO_Y23,
@@ -520,7 +520,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y25,
 	EXYNOS4X12_GPIO_Y26,
 	EXYNOS4X12_GPIO_Y27,
-	EXYNOS4X12_GPIO_Y30,		/* 256 0x100 */
+	EXYNOS4X12_GPIO_Y30,		/* 184 0xb8 */
 	EXYNOS4X12_GPIO_Y31,
 	EXYNOS4X12_GPIO_Y32,
 	EXYNOS4X12_GPIO_Y33,
@@ -528,7 +528,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y35,
 	EXYNOS4X12_GPIO_Y36,
 	EXYNOS4X12_GPIO_Y37,
-	EXYNOS4X12_GPIO_Y40,		/* 264 0x108 */
+	EXYNOS4X12_GPIO_Y40,		/* 192 0xc0 */
 	EXYNOS4X12_GPIO_Y41,
 	EXYNOS4X12_GPIO_Y42,
 	EXYNOS4X12_GPIO_Y43,
@@ -536,7 +536,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y45,
 	EXYNOS4X12_GPIO_Y46,
 	EXYNOS4X12_GPIO_Y47,
-	EXYNOS4X12_GPIO_Y50,		/* 272 0x110 */
+	EXYNOS4X12_GPIO_Y50,		/* 200 0xc8 */
 	EXYNOS4X12_GPIO_Y51,
 	EXYNOS4X12_GPIO_Y52,
 	EXYNOS4X12_GPIO_Y53,
@@ -544,7 +544,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y55,
 	EXYNOS4X12_GPIO_Y56,
 	EXYNOS4X12_GPIO_Y57,
-	EXYNOS4X12_GPIO_Y60,		/* 280 0x118 */
+	EXYNOS4X12_GPIO_Y60,		/* 208 0xd0 */
 	EXYNOS4X12_GPIO_Y61,
 	EXYNOS4X12_GPIO_Y62,
 	EXYNOS4X12_GPIO_Y63,
@@ -552,7 +552,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y65,
 	EXYNOS4X12_GPIO_Y66,
 	EXYNOS4X12_GPIO_Y67,
-	EXYNOS4X12_GPIO_M00 = 312,	/* 312 0xF0 */
+	EXYNOS4X12_GPIO_M00,		/* 216 0xd8 */
 	EXYNOS4X12_GPIO_M01,
 	EXYNOS4X12_GPIO_M02,
 	EXYNOS4X12_GPIO_M03,
@@ -560,7 +560,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M05,
 	EXYNOS4X12_GPIO_M06,
 	EXYNOS4X12_GPIO_M07,
-	EXYNOS4X12_GPIO_M10,		/* 320 0xF8 */
+	EXYNOS4X12_GPIO_M10,		/* 224 0xe0 */
 	EXYNOS4X12_GPIO_M11,
 	EXYNOS4X12_GPIO_M12,
 	EXYNOS4X12_GPIO_M13,
@@ -568,7 +568,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M15,
 	EXYNOS4X12_GPIO_M16,
 	EXYNOS4X12_GPIO_M17,
-	EXYNOS4X12_GPIO_M20,		/* 328 0x100 */
+	EXYNOS4X12_GPIO_M20,		/* 232 0xe8 */
 	EXYNOS4X12_GPIO_M21,
 	EXYNOS4X12_GPIO_M22,
 	EXYNOS4X12_GPIO_M23,
@@ -576,7 +576,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M25,
 	EXYNOS4X12_GPIO_M26,
 	EXYNOS4X12_GPIO_M27,
-	EXYNOS4X12_GPIO_M30,		/* 336 0x108 */
+	EXYNOS4X12_GPIO_M30,		/* 240 0xf0 */
 	EXYNOS4X12_GPIO_M31,
 	EXYNOS4X12_GPIO_M32,
 	EXYNOS4X12_GPIO_M33,
@@ -584,7 +584,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M35,
 	EXYNOS4X12_GPIO_M36,
 	EXYNOS4X12_GPIO_M37,
-	EXYNOS4X12_GPIO_M40,		/* 344 0x110 */
+	EXYNOS4X12_GPIO_M40,		/* 248 0xf8 */
 	EXYNOS4X12_GPIO_M41,
 	EXYNOS4X12_GPIO_M42,
 	EXYNOS4X12_GPIO_M43,
@@ -592,7 +592,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M45,
 	EXYNOS4X12_GPIO_M46,
 	EXYNOS4X12_GPIO_M47,
-	EXYNOS4X12_GPIO_X00 = 928,	/* 928 0x3A0 */
+	EXYNOS4X12_GPIO_X00,		/* 256 0x100 */
 	EXYNOS4X12_GPIO_X01,
 	EXYNOS4X12_GPIO_X02,
 	EXYNOS4X12_GPIO_X03,
@@ -600,7 +600,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_X05,
 	EXYNOS4X12_GPIO_X06,
 	EXYNOS4X12_GPIO_X07,
-	EXYNOS4X12_GPIO_X10,		/* 936 0x3A8 */
+	EXYNOS4X12_GPIO_X10,		/* 264 0x108 */
 	EXYNOS4X12_GPIO_X11,
 	EXYNOS4X12_GPIO_X12,
 	EXYNOS4X12_GPIO_X13,
@@ -608,7 +608,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_X15,
 	EXYNOS4X12_GPIO_X16,
 	EXYNOS4X12_GPIO_X17,
-	EXYNOS4X12_GPIO_X20,		/* 944 0x3B0 */
+	EXYNOS4X12_GPIO_X20,		/* 272 0x110 */
 	EXYNOS4X12_GPIO_X21,
 	EXYNOS4X12_GPIO_X22,
 	EXYNOS4X12_GPIO_X23,
@@ -616,7 +616,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_X25,
 	EXYNOS4X12_GPIO_X26,
 	EXYNOS4X12_GPIO_X27,
-	EXYNOS4X12_GPIO_X30,		/* 952 0x3B8 */
+	EXYNOS4X12_GPIO_X30,		/* 280 0x118 */
 	EXYNOS4X12_GPIO_X31,
 	EXYNOS4X12_GPIO_X32,
 	EXYNOS4X12_GPIO_X33,
@@ -626,7 +626,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_X37,
 
 	/* GPIO_PART3_STARTS */
-	EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
 	EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
 	EXYNOS4X12_GPIO_Z1,
 	EXYNOS4X12_GPIO_Z2,
@@ -637,7 +637,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Z7,
 
 	/* GPIO_PART4_STARTS */
-	EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
 	EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
 	EXYNOS4X12_GPIO_V01,
 	EXYNOS4X12_GPIO_V02,
@@ -646,7 +646,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_V05,
 	EXYNOS4X12_GPIO_V06,
 	EXYNOS4X12_GPIO_V07,
-	EXYNOS4X12_GPIO_V10,		/* 976 0x3D0 */
+	EXYNOS4X12_GPIO_V10,		/* 304 0x130 */
 	EXYNOS4X12_GPIO_V11,
 	EXYNOS4X12_GPIO_V12,
 	EXYNOS4X12_GPIO_V13,
@@ -654,7 +654,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_V15,
 	EXYNOS4X12_GPIO_V16,
 	EXYNOS4X12_GPIO_V17,
-	EXYNOS4X12_GPIO_V20 = 992,	/* 992 0x3E0 */
+	EXYNOS4X12_GPIO_V20,		/* 312 0x138 */
 	EXYNOS4X12_GPIO_V21,
 	EXYNOS4X12_GPIO_V22,
 	EXYNOS4X12_GPIO_V23,
@@ -662,7 +662,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_V25,
 	EXYNOS4X12_GPIO_V26,
 	EXYNOS4X12_GPIO_V27,
-	EXYNOS4X12_GPIO_V30 = 1000,	/* 1000 0x3E8 */
+	EXYNOS4X12_GPIO_V30,		/* 320 0x140 */
 	EXYNOS4X12_GPIO_V31,
 	EXYNOS4X12_GPIO_V32,
 	EXYNOS4X12_GPIO_V33,
@@ -670,7 +670,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_V35,
 	EXYNOS4X12_GPIO_V36,
 	EXYNOS4X12_GPIO_V37,
-	EXYNOS4X12_GPIO_V40 = 1016,	/* 1016 0x3F8 */
+	EXYNOS4X12_GPIO_V40,		/* 328 0x148 */
 	EXYNOS4X12_GPIO_V41,
 	EXYNOS4X12_GPIO_V42,
 	EXYNOS4X12_GPIO_V43,
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index bd6f2d2..2de205e 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -682,8 +682,7 @@ enum s5pc110_gpio_pin {
 	S5PC110_GPIO_MP285,
 	S5PC110_GPIO_MP286,
 	S5PC110_GPIO_MP287,
-	S5PC110_GPIO_RES,
-	S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)),
+	S5PC110_GPIO_H00,
 	S5PC110_GPIO_H01,
 	S5PC110_GPIO_H02,
 	S5PC110_GPIO_H03,
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 99f2dd8..13d74eb 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -6,8 +6,15 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define S5P_GPIO_GET_PIN(x)	(x % GPIO_PER_BANK)
 
@@ -26,100 +33,45 @@
 #define RATE_MASK(gpio)		(0x1 << (gpio + 16))
 #define RATE_SET(gpio)			(0x1 << (gpio + 16))
 
-#define name_to_gpio(n) s5p_name_to_gpio(n)
-static inline int s5p_name_to_gpio(const char *name)
+#define GPIO_NAME_SIZE			20
+
+/* Platform data for each bank */
+struct exynos_gpio_platdata {
+	struct s5p_gpio_bank *bank;
+	const char *bank_name;	/* Name of port, e.g. 'gpa0" */
+};
+
+/* Information about each bank at run-time */
+struct exynos_bank_info {
+	char label[GPIO_PER_BANK][GPIO_NAME_SIZE];
+	struct s5p_gpio_bank *bank;
+};
+
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
 {
-	unsigned num, irregular_set_number, irregular_bank_base;
-	const struct gpio_name_num_table *tabp;
-	char this_bank, bank_name, irregular_bank_name;
-	char *endp;
-
-	/*
-	 * The gpio name starts with either 'g' or 'gp' followed by the bank
-	 * name character. Skip one or two characters depending on the prefix.
-	 */
-	if (name[0] == 'g' && name[1] == 'p')
-		name += 2;
-	else if (name[0] == 'g')
-		name++;
-	else
-		return -1; /* Name must start with 'g' */
-
-	bank_name = *name++;
-	if (!*name)
-		return -1; /* At least one digit is required/expected. */
-
-	/*
-	 * On both exynos5 and exynos5420 architectures there is a bank of
-	 * GPIOs which does not fall into the regular address pattern. Those
-	 * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
-	 * assignments help to handle these irregularities.
-	 */
-#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
-	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420()) {
-			tabp = exynos5420_gpio_table;
-			irregular_bank_name = 'y';
-			irregular_set_number = '7';
-			irregular_bank_base = EXYNOS5420_GPIO_Y70;
-		} else {
-			tabp = exynos5_gpio_table;
-			irregular_bank_name = 'c';
-			irregular_set_number = '4';
-			irregular_bank_base = EXYNOS5_GPIO_C40;
-		}
-	} else {
-		if (proid_is_exynos4412())
-			tabp = exynos4x12_gpio_table;
-		else
-			tabp = exynos4_gpio_table;
-		irregular_bank_name = 0;
-		irregular_set_number = 0;
-		irregular_bank_base = 0;
-	}
-#else
-	if (cpu_is_s5pc110())
-		tabp = s5pc110_gpio_table;
-	else
-		tabp = s5pc100_gpio_table;
-	irregular_bank_name = 0;
-	irregular_set_number = 0;
-	irregular_bank_base = 0;
-#endif
+	const struct gpio_info *data;
+	unsigned int upto;
+	int i, count;
 
-	this_bank = tabp->bank;
-	do {
-		if (bank_name == this_bank) {
-			unsigned pin_index; /* pin number within the bank */
-			if ((bank_name == irregular_bank_name) &&
-			    (name[0] == irregular_set_number)) {
-				pin_index = name[1] - '0';
-				/* Irregular sets have 8 pins. */
-				if (pin_index >= GPIO_PER_BANK)
-					return -1;
-				num = irregular_bank_base + pin_index;
-			} else {
-				pin_index = simple_strtoul(name, &endp, 8);
-				pin_index -= tabp->bank_offset;
-				/*
-				 * Sanity check: bunk 'z' has no set number,
-				 * for all other banks there must be exactly
-				 * two octal digits, and the resulting number
-				 * should not exceed the number of pins in the
-				 * bank.
-				 */
-				if (((bank_name != 'z') && !name[1]) ||
-				    *endp ||
-				    (pin_index >= tabp->bank_size))
-					return -1;
-				num = tabp->base + pin_index;
-			}
-			return num;
+	data = get_gpio_data();
+	count = get_bank_num();
+	upto = 0;
+
+	for (i = 0; i < count; i++) {
+		debug("i=%d, upto=%d\n", i, upto);
+		if (gpio < data->max_gpio) {
+			struct s5p_gpio_bank *bank;
+			bank = (struct s5p_gpio_bank *)data->reg_addr;
+			bank += (gpio - upto) / GPIO_PER_BANK;
+			debug("gpio=%d, bank=%p\n", gpio, bank);
+			return bank;
 		}
-		this_bank = (++tabp)->bank;
-	} while (this_bank);
 
-	return -1;
+		upto = data->max_gpio;
+		data++;
+	}
+
+	return NULL;
 }
 
 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
@@ -143,16 +95,23 @@ static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
 	writel(value, &bank->dat);
 }
 
-static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank,
-				      int gpio, int en)
+#ifdef CONFIG_SPL_BUILD
+/* Common GPIO API - SPL does not support driver model yet */
+int gpio_set_value(unsigned gpio, int value)
 {
-	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
-	s5p_gpio_set_value(bank, gpio, en);
-}
+	s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
+			   s5p_gpio_get_pin(gpio), value);
 
-static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
+	return 0;
+}
+#else
+static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio)
 {
-	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
+	unsigned int value;
+
+	value = readl(&bank->con);
+	value &= CON_MASK(gpio);
+	return CON_SFR_UNSHIFT(value, gpio);
 }
 
 static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
@@ -162,6 +121,7 @@ static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
 	value = readl(&bank->dat);
 	return !!(value & DAT_MASK(gpio));
 }
+#endif /* CONFIG_SPL_BUILD */
 
 static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 {
@@ -222,78 +182,156 @@ static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 	writel(value, &bank->drv);
 }
 
-static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
+int s5p_gpio_get_pin(unsigned gpio)
 {
-	const struct gpio_info *data;
-	unsigned int upto;
-	int i, count;
+	return S5P_GPIO_GET_PIN(gpio);
+}
 
-	data = get_gpio_data();
-	count = get_bank_num();
-	upto = 0;
+/* Driver model interface */
+#ifndef CONFIG_SPL_BUILD
+static int exynos_gpio_get_state(struct udevice *dev, unsigned int offset,
+				char *buf, int bufsize)
+{
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	const char *label;
+	bool is_output;
+	int size;
+	int cfg;
+
+	label = state->label[offset];
+	cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
+	is_output = cfg == S5P_GPIO_OUTPUT;
+	size = snprintf(buf, bufsize, "%s%d: ",
+			uc_priv->bank_name ? uc_priv->bank_name : "", offset);
+	buf += size;
+	bufsize -= size;
+	if (is_output || cfg == S5P_GPIO_INPUT) {
+		snprintf(buf, bufsize, "%s: %d [%c]%s%s",
+			 is_output ? "out" : " in",
+			 s5p_gpio_get_value(state->bank, offset),
+			 *label ? 'x' : ' ',
+			 *label ? " " : "",
+			 label);
+	} else {
+		snprintf(buf, bufsize, "sfpio");
+	}
 
-	for (i = 0; i < count; i++) {
-		debug("i=%d, upto=%d\n", i, upto);
-		if (gpio < data->max_gpio) {
-			struct s5p_gpio_bank *bank;
-			bank = (struct s5p_gpio_bank *)data->reg_addr;
-			bank += (gpio - upto) / GPIO_PER_BANK;
-			debug("gpio=%d, bank=%p\n", gpio, bank);
-			return bank;
-		}
+	return 0;
+}
 
-		upto = data->max_gpio;
-		data++;
+static int check_reserved(struct udevice *dev, unsigned offset,
+			  const char *func)
+{
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+	if (!*state->label[offset]) {
+		printf("exynos_gpio: %s: error: gpio %s%d not reserved\n",
+		       func, uc_priv->bank_name, offset);
+		return -EPERM;
 	}
 
-	return NULL;
+	return 0;
 }
 
-int s5p_gpio_get_pin(unsigned gpio)
+/* set GPIO pin 'gpio' as an input */
+static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
-	return S5P_GPIO_GET_PIN(gpio);
-}
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	int ret;
 
-/* Common GPIO API */
+	ret = check_reserved(dev, offset, __func__);
+	if (ret)
+		return ret;
+
+	/* Configure GPIO direction as input. */
+	s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);
 
-int gpio_request(unsigned gpio, const char *label)
-{
 	return 0;
 }
 
-int gpio_free(unsigned gpio)
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
 {
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	int ret;
+
+	ret = check_reserved(dev, offset, __func__);
+	if (ret)
+		return ret;
+
+	/* Configure GPIO output value. */
+	s5p_gpio_set_value(state->bank, offset, value);
+
+	/* Configure GPIO direction as output. */
+	s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT);
+
 	return 0;
 }
 
-int gpio_direction_input(unsigned gpio)
+/* read GPIO IN value of pin 'gpio' */
+static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
 {
-	s5p_gpio_direction_input(s5p_gpio_get_bank(gpio),
-				s5p_gpio_get_pin(gpio));
-	return 0;
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	int ret;
+
+	ret = check_reserved(dev, offset, __func__);
+	if (ret)
+		return ret;
+
+	return s5p_gpio_get_value(state->bank, offset);
 }
 
-int gpio_direction_output(unsigned gpio, int value)
+/* write GPIO OUT value to pin 'gpio' */
+static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
+				 int value)
 {
-	s5p_gpio_direction_output(s5p_gpio_get_bank(gpio),
-				 s5p_gpio_get_pin(gpio), value);
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	int ret;
+
+	ret = check_reserved(dev, offset, __func__);
+	if (ret)
+		return ret;
+
+	s5p_gpio_set_value(state->bank, offset, value);
+
 	return 0;
 }
 
-int gpio_get_value(unsigned gpio)
+static int exynos_gpio_request(struct udevice *dev, unsigned offset,
+			      const char *label)
 {
-	return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio),
-				       s5p_gpio_get_pin(gpio));
+	struct exynos_bank_info *state = dev_get_priv(dev);
+
+	if (*state->label[offset])
+		return -EBUSY;
+
+	strncpy(state->label[offset], label, GPIO_NAME_SIZE);
+	state->label[offset][GPIO_NAME_SIZE - 1] = '\0';
+
+	return 0;
 }
 
-int gpio_set_value(unsigned gpio, int value)
+static int exynos_gpio_free(struct udevice *dev, unsigned offset)
 {
-	s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
-			  s5p_gpio_get_pin(gpio), value);
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	int ret;
+
+	ret = check_reserved(dev, offset, __func__);
+	if (ret)
+		return ret;
+	state->label[offset][0] = '\0';
 
 	return 0;
 }
+#endif /* nCONFIG_SPL_BUILD */
 
+/*
+ * There is no common GPIO API for pull, drv, pin, rate (yet). These
+ * functions are kept here to preserve function ordering for review.
+ */
 void gpio_set_pull(int gpio, int mode)
 {
 	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
@@ -317,3 +355,117 @@ void gpio_set_rate(int gpio, int mode)
 	s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
 			  s5p_gpio_get_pin(gpio), mode);
 }
+
+#ifndef CONFIG_SPL_BUILD
+static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	int cfg;
+
+	if (!*state->label[offset])
+		return GPIOF_UNUSED;
+	cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
+	if (cfg == S5P_GPIO_OUTPUT)
+		return GPIOF_OUTPUT;
+	else if (cfg == S5P_GPIO_INPUT)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_exynos_ops = {
+	.request		= exynos_gpio_request,
+	.free			= exynos_gpio_free,
+	.direction_input	= exynos_gpio_direction_input,
+	.direction_output	= exynos_gpio_direction_output,
+	.get_value		= exynos_gpio_get_value,
+	.set_value		= exynos_gpio_set_value,
+	.get_function		= exynos_gpio_get_function,
+	.get_state		= exynos_gpio_get_state,
+};
+
+static int gpio_exynos_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	struct exynos_bank_info *priv = dev->priv;
+	struct exynos_gpio_platdata *plat = dev->platdata;
+
+	/* Only child devices have ports */
+	if (!plat)
+		return 0;
+
+	priv->bank = plat->bank;
+
+	uc_priv->gpio_count = GPIO_PER_BANK;
+	uc_priv->bank_name = plat->bank_name;
+
+	return 0;
+}
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */
+static int gpio_exynos_bind(struct udevice *parent)
+{
+	struct exynos_gpio_platdata *plat = parent->platdata;
+	struct s5p_gpio_bank *bank, *base;
+	const void *blob = gd->fdt_blob;
+	int node;
+
+	/* If this is a child device, there is nothing to do here */
+	if (plat)
+		return 0;
+
+	base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
+						   parent->of_offset, "reg");
+	for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
+	     node > 0;
+	     node = fdt_next_subnode(blob, node), bank++) {
+		struct exynos_gpio_platdata *plat;
+		struct udevice *dev;
+		fdt_addr_t reg;
+		int ret;
+
+		if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+			continue;
+		plat = calloc(1, sizeof(*plat));
+		if (!plat)
+			return -ENOMEM;
+		reg = fdtdec_get_addr(blob, node, "reg");
+		if (reg != FDT_ADDR_T_NONE)
+			bank = (struct s5p_gpio_bank *)((ulong)base + reg);
+		plat->bank = bank;
+		plat->bank_name = fdt_get_name(blob, node, NULL);
+		debug("dev at %p: %s\n", bank, plat->bank_name);
+
+		ret = device_bind(parent, parent->driver,
+					plat->bank_name, plat, -1, &dev);
+		if (ret)
+			return ret;
+		dev->of_offset = parent->of_offset;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id exynos_gpio_ids[] = {
+	{ .compatible = "samsung,s5pc100-pinctrl" },
+	{ .compatible = "samsung,s5pc110-pinctrl" },
+	{ .compatible = "samsung,exynos4210-pinctrl" },
+	{ .compatible = "samsung,exynos4x12-pinctrl" },
+	{ .compatible = "samsung,exynos5250-pinctrl" },
+	{ .compatible = "samsung,exynos5420-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_exynos) = {
+	.name	= "gpio_exynos",
+	.id	= UCLASS_GPIO,
+	.of_match = exynos_gpio_ids,
+	.bind	= gpio_exynos_bind,
+	.probe = gpio_exynos_probe,
+	.priv_auto_alloc_size = sizeof(struct exynos_bank_info),
+	.ops	= &gpio_exynos_ops,
+};
+#endif
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 371f32d..4a4b22b 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -17,6 +17,10 @@
 #include <linux/sizes.h>
 
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index fa0e737..fb1a7db 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -287,5 +287,8 @@
 #define CONFIG_OF_LIBFDT
 
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index a7eb33e..424e130 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -224,5 +224,8 @@
 #define CONFIG_OF_LIBFDT
 
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
 
 #endif	/* __CONFIG_H */
