From patchwork Sun Oct 19 18:43:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 400826 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5526914007F for ; Mon, 20 Oct 2014 05:44:32 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DCA404B608; Sun, 19 Oct 2014 20:44:01 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0wT9AgyKFMcA; Sun, 19 Oct 2014 20:44:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E1804B606; Sun, 19 Oct 2014 20:44:01 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8D6CD4B606 for ; Sun, 19 Oct 2014 20:43:50 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YZTRVQBA98Fh for ; Sun, 19 Oct 2014 20:43:50 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTPS id 35C8E4B601 for ; Sun, 19 Oct 2014 20:43:47 +0200 (CEST) Received: from mail.nefkom.net (unknown [192.168.8.184]) by mail-out.m-online.net (Postfix) with ESMTP id 3jLVNy51dlz3hjYP; Sun, 19 Oct 2014 20:43:46 +0200 (CEST) X-Auth-Info: Oq9IF05jfRqglC/ZcQu3aL3FME9vBrBTaz5Iy2I4icg= Received: from chi.lan (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3jLVNy0KBVzvdWV; Sun, 19 Oct 2014 20:43:45 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Sun, 19 Oct 2014 20:43:34 +0200 Message-Id: <1413744219-6859-2-git-send-email-marex@denx.de> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1413744219-6859-1-git-send-email-marex@denx.de> References: <1413744219-6859-1-git-send-email-marex@denx.de> Cc: Marek Vasut , Pavel Machek , Chin Liang See , Tom Rini , Dinh Nguyen Subject: [U-Boot] [PATCH 2/7] spi: altera: Clean up bit definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Clean up the definitions of bits in the Altera SPI driver, there is no need to put braces around numbers afterall. No functional change. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Jagannadha Sutradharudu Teki --- drivers/spi/altera_spi.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 13191f3..21f90fc 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -21,19 +21,19 @@ struct altera_spi_regs { u32 slave_sel; }; -#define ALTERA_SPI_STATUS_ROE_MSK (0x8) -#define ALTERA_SPI_STATUS_TOE_MSK (0x10) -#define ALTERA_SPI_STATUS_TMT_MSK (0x20) -#define ALTERA_SPI_STATUS_TRDY_MSK (0x40) -#define ALTERA_SPI_STATUS_RRDY_MSK (0x80) -#define ALTERA_SPI_STATUS_E_MSK (0x100) - -#define ALTERA_SPI_CONTROL_IROE_MSK (0x8) -#define ALTERA_SPI_CONTROL_ITOE_MSK (0x10) -#define ALTERA_SPI_CONTROL_ITRDY_MSK (0x40) -#define ALTERA_SPI_CONTROL_IRRDY_MSK (0x80) -#define ALTERA_SPI_CONTROL_IE_MSK (0x100) -#define ALTERA_SPI_CONTROL_SSO_MSK (0x400) +#define ALTERA_SPI_STATUS_ROE_MSK (1 << 3) +#define ALTERA_SPI_STATUS_TOE_MSK (1 << 4) +#define ALTERA_SPI_STATUS_TMT_MSK (1 << 5) +#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6) +#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7) +#define ALTERA_SPI_STATUS_E_MSK (1 << 8) + +#define ALTERA_SPI_CONTROL_IROE_MSK (1 << 3) +#define ALTERA_SPI_CONTROL_ITOE_MSK (1 << 4) +#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 << 6) +#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 << 7) +#define ALTERA_SPI_CONTROL_IE_MSK (1 << 8) +#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10) #ifndef CONFIG_SYS_ALTERA_SPI_LIST #define CONFIG_SYS_ALTERA_SPI_LIST { CONFIG_SYS_SPI_BASE }