From patchwork Wed Oct 15 08:37:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 399810 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 61E5114007B for ; Wed, 15 Oct 2014 19:39:37 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8D2C0A77E1; Wed, 15 Oct 2014 10:39:30 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HR9Wq3oNatpn; Wed, 15 Oct 2014 10:39:30 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D3CC0B3797; Wed, 15 Oct 2014 10:39:22 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 86FA8A775B for ; Wed, 15 Oct 2014 10:39:05 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6G2hqRerAtM2 for ; Wed, 15 Oct 2014 10:39:05 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qa0-f74.google.com (mail-qa0-f74.google.com [209.85.216.74]) by theia.denx.de (Postfix) with ESMTPS id 0A07BA775E for ; Wed, 15 Oct 2014 10:39:01 +0200 (CEST) Received: by mail-qa0-f74.google.com with SMTP id x12so56903qac.3 for ; Wed, 15 Oct 2014 01:38:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t9CM4fujv0h4O+zZ0I/Cv34VYtZLuLzGHOgar7RFX6g=; b=doe+Gzamm7KizAI6/e+mB/Yi8ey9Nc8qlwm62N8fApwS/sXBrVA6ohF3F3huhBpCjk Y0e/7OyDemeCSvy08OnbAiyfyLMQJ/QJU+OqGVD9D9qyqhBGnij67HyAbjGL7AXwz40v o4TZnGBfH4q4IcnThybgw/Qa8nE+v4RzRBOszkoZ1hvHlKlr2woulHALXBp+FPoHl1hr RYQDyI4tGHnce5ZRtmEjRM9d6fd8Z+LHhpLsbTUX2jZLtm1F4618QJUTqKLLGUqu27Xh FSVsUSJYHLn5D64NVsESGZwx2kdBtDwSGXOvLfZGVYFIBN16s5ycz5xV99n6ogfD+27h 0rhQ== X-Gm-Message-State: ALoCoQlfux9cBUSqf5f+40GvrZuXOQQtM+Q/I9RCJl8Wokgk+v5fyKsY0kt/4CvUBNsf0Ql/yGIx X-Received: by 10.236.198.165 with SMTP id v25mr7359271yhn.51.1413362339863; Wed, 15 Oct 2014 01:38:59 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id t28si940808yhb.4.2014.10.15.01.38.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Oct 2014 01:38:59 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id DfT7R89K.1; Wed, 15 Oct 2014 01:38:59 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id E7A8A220F6A; Wed, 15 Oct 2014 02:38:58 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 15 Oct 2014 02:37:54 -0600 Message-Id: <1413362282-25451-5-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1413362282-25451-1-git-send-email-sjg@chromium.org> References: <1413362282-25451-1-git-send-email-sjg@chromium.org> Cc: u-boot-review@google.com, Tom Warren Subject: [U-Boot] [PATCH v9 04/12] dm: exynos: dts: Adjust device tree files for U-Boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The pinctrl bindings used by Linux are an incomplete description of the hardware. It is possible in most cases to determine the register address of each, but not in all cases. By adding an additional property we can fix this, and avoid adding a table to U-Boot for every single Exynos SOC. Signed-off-by: Simon Glass --- Changes in v9: None Changes in v8: - Add missing special case reg property for exynos5420 GPX0 Changes in v7: None Changes in v6: - Move U-Boot changes into their own file - Use exynos54xx everywhere instead of exynos5420 Changes in v5: None Changes in v4: None arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 27 ++++++++++++++++++ arch/arm/dts/exynos4210-pinctrl.dtsi | 2 ++ arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 46 ++++++++++++++++++++++++++++++ arch/arm/dts/exynos4x12-pinctrl.dtsi | 2 ++ arch/arm/dts/exynos5250-pinctrl-uboot.dtsi | 40 ++++++++++++++++++++++++++ arch/arm/dts/exynos5250-pinctrl.dtsi | 2 ++ arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi | 40 ++++++++++++++++++++++++++ arch/arm/dts/exynos54xx-pinctrl.dtsi | 2 ++ arch/arm/dts/exynos54xx.dtsi | 1 + 9 files changed, 162 insertions(+) create mode 100644 arch/arm/dts/exynos4210-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos5250-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi new file mode 100644 index 0000000..ee071c1 --- /dev/null +++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi @@ -0,0 +1,27 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos4210-pinctrl"; + }; + + pinctrl_1: pinctrl@11000000 { + #address-cells = <1>; + #size-cells = <0>; + gpy0: gpy0 { + reg = <0xc00>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos4210-pinctrl.dtsi b/arch/arm/dts/exynos4210-pinctrl.dtsi index bda17f7..87f162b 100644 --- a/arch/arm/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/dts/exynos4210-pinctrl.dtsi @@ -14,6 +14,8 @@ * published by the Free Software Foundation. */ +#include "exynos4210-pinctrl-uboot.dtsi" + / { pinctrl@11400000 { gpa0: gpa0 { diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi new file mode 100644 index 0000000..c02796d --- /dev/null +++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi @@ -0,0 +1,46 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + gpf0: gpf0 { + reg = <0xc180>; + }; + gpj0: gpj0 { + reg = <0x240>; + }; + }; + + pinctrl_1: pinctrl@11000000 { + #address-cells = <1>; + #size-cells = <0>; + gpk0: gpk0 { + reg = <0x40>; + }; + gpm0: gpm0 { + reg = <0x260>; + }; + gpy0: gpy0 { + reg = <0x120>; + }; + gpx0: gpx0 { + reg = <0xc00>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + + pinctrl_3: pinctrl@106E0000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos4x12-pinctrl.dtsi b/arch/arm/dts/exynos4x12-pinctrl.dtsi index 93f3998..f40de1f 100644 --- a/arch/arm/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/dts/exynos4x12-pinctrl.dtsi @@ -12,6 +12,8 @@ * published by the Free Software Foundation. */ +#include "exynos4x12-pinctrl-uboot.dtsi" + / { pinctrl@11400000 { gpa0: gpa0 { diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi new file mode 100644 index 0000000..7edb0ca --- /dev/null +++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi @@ -0,0 +1,40 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + gpc4: gpc4 { + reg = <0x2e0>; + }; + gpx0: gpx0 { + reg = <0xc00>; + }; + }; + + pinctrl_1: pinctrl@13400000 { + #address-cells = <1>; + #size-cells = <0>; + }; + + pinctrl_2: pinctrl@10d10000 { + #address-cells = <1>; + #size-cells = <0>; + gpv2: gpv2 { + reg = <0x060>; + }; + gpv4: gpv4 { + reg = <0xc0>; + }; + }; + + pinctrl_3: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos5250-pinctrl.dtsi b/arch/arm/dts/exynos5250-pinctrl.dtsi index 67755a1..706b888 100644 --- a/arch/arm/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/dts/exynos5250-pinctrl.dtsi @@ -12,6 +12,8 @@ * published by the Free Software Foundation. */ +#include "exynos5250-pinctrl-uboot.dtsi" + / { pinctrl@11400000 { gpa0: gpa0 { diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi new file mode 100644 index 0000000..5a86211 --- /dev/null +++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi @@ -0,0 +1,40 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + /* + * Replicate the ordering of arch/arm/include/asm/arch-exynos/gpio.h + * TODO(sjg@chromium.org): This ordering ceases to matter once GPIO + * numbers are not needed in U-Boot for exynos. + */ + pinctrl@14010000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@13400000 { + #address-cells = <1>; + #size-cells = <0>; + gpy7 { + }; + + gpx0 { + reg = <0xc00>; + }; + }; + pinctrl@13410000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@14000000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos54xx-pinctrl.dtsi b/arch/arm/dts/exynos54xx-pinctrl.dtsi index b3e63d1..775d956 100644 --- a/arch/arm/dts/exynos54xx-pinctrl.dtsi +++ b/arch/arm/dts/exynos54xx-pinctrl.dtsi @@ -12,6 +12,8 @@ * published by the Free Software Foundation. */ +#include "exynos54xx-pinctrl-uboot.dtsi" + / { pinctrl@13400000 { gpy7: gpy7 { diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index 887b034..916cf3a 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -6,6 +6,7 @@ */ #include "exynos5.dtsi" +#include "exynos54xx-pinctrl.dtsi" / { config {