From patchwork Wed Oct 15 02:53:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Qiang X-Patchwork-Id: 399685 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 431E21400B0 for ; Wed, 15 Oct 2014 13:54:12 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C3C7E4B761; Wed, 15 Oct 2014 04:54:08 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eEVy9wH+PYlg; Wed, 15 Oct 2014 04:54:08 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D2EC24B759; Wed, 15 Oct 2014 04:54:07 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 320AE4B759 for ; Wed, 15 Oct 2014 04:54:02 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id S112O3HtyjAe for ; Wed, 15 Oct 2014 04:54:02 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1bon0142.outbound.protection.outlook.com [157.56.111.142]) by theia.denx.de (Postfix) with ESMTPS id A74D74B758 for ; Wed, 15 Oct 2014 04:53:57 +0200 (CEST) Received: from CH1PR03CA006.namprd03.prod.outlook.com (10.255.156.151) by DM2PR0301MB0765.namprd03.prod.outlook.com (25.160.97.149) with Microsoft SMTP Server (TLS) id 15.0.1049.19; Wed, 15 Oct 2014 02:53:55 +0000 Received: from BY2FFO11FD047.protection.gbl (10.255.156.132) by CH1PR03CA006.outlook.office365.com (10.255.156.151) with Microsoft SMTP Server (TLS) id 15.0.1049.19 via Frontend Transport; Wed, 15 Oct 2014 02:53:54 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD047.mail.protection.outlook.com (10.1.15.175) with Microsoft SMTP Server (TLS) id 15.0.1039.16 via Frontend Transport; Wed, 15 Oct 2014 02:53:54 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s9F2rpmF009970; Tue, 14 Oct 2014 19:53:52 -0700 From: Zhao Qiang To: , Date: Wed, 15 Oct 2014 10:53:18 +0800 Message-ID: <1413341598-13907-1-git-send-email-B45475@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(199003)(189002)(46102003)(92726001)(80022003)(92566001)(93916002)(26826002)(84676001)(99396003)(104166001)(102836001)(120916001)(85852003)(6806004)(88136002)(21056001)(44976005)(19580395003)(19580405001)(89996001)(76482002)(4396001)(50226001)(97736003)(87936001)(87286001)(68736004)(69596002)(62966002)(105606002)(50986999)(104016003)(95666004)(77156001)(36756003)(50466002)(64706001)(229853001)(85306004)(47776003)(20776003)(107046002)(48376002)(81156004)(106466001)(31966008)(42262002); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0765; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0765; X-Forefront-PRVS: 0365C0E14B Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=qiang.zhao@freescale.com; X-OriginatorOrg: freescale.com Cc: Zhao Qiang Subject: [U-Boot] [PATCH v3] powerpc/mpc85xx: modify erratum A007186 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de T2080 v1.0 has this errata while v1.1 has fixed this errata by hardware, add a new function has_errata_a007186 to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first, if the sil has errata a007186, then run the errata code, if not, doesn't run the code. Signed-off-by: Zhao Qiang --- Changes for v2: - use has_errata_a007186 instead of not_has_errata_a007186 Changes for v3: - use "if (has_erratum_a007186() && sel == 0x01 || sel == 0x02) {" - instead of "if (has_erratum_a007186()) { if(sel == 0x01 || sel == 0x02)" arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 ++- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 3 ++- arch/powerpc/include/asm/fsl_errata.h | 22 ++++++++++++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3a04a89..0774461 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -270,7 +270,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum USB14 enabled\n"); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 - puts("Work-around for Erratum A007186 enabled\n"); + if (has_erratum_a007186()) + puts("Work-around for Erratum A007186 enabled\n"); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index d1fc76a..b8ee6e0 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "fsl_corenet2_serdes.h" #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -208,7 +209,7 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK; - if (sel == 0x01 || sel == 0x02) { + if (has_erratum_a007186() && sel == 0x01 || sel == 0x02) { for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) { pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); debug("A007186: pll_num=%x pllcr0=%x\n", diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 64da4bb..655072b 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -82,3 +82,25 @@ static inline bool has_erratum_a007075(void) return false; } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 +static inline bool has_erratum_a007186(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + case SVR_T4160: + case SVR_T4080: + case SVR_B4860: + case SVR_B4420: + case SVR_T2081: + return true; + case SVR_T2080: + return IS_SVR_REV(svr, 1, 0); + } + + return false; +} +#endif