From patchwork Mon Sep 29 19:34:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 394588 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 63CDE140111 for ; Tue, 30 Sep 2014 05:38:05 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3F39CA7435; Mon, 29 Sep 2014 21:37:55 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id buiZtbjlF6eJ; Mon, 29 Sep 2014 21:37:55 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 611FAA7408; Mon, 29 Sep 2014 21:37:46 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ED60D4B61F for ; Mon, 29 Sep 2014 21:37:31 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fqsrDCwJkRRU for ; Mon, 29 Sep 2014 21:37:31 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oi0-f74.google.com (mail-oi0-f74.google.com [209.85.218.74]) by theia.denx.de (Postfix) with ESMTPS id 95BCA4B61C for ; Mon, 29 Sep 2014 21:37:27 +0200 (CEST) Received: by mail-oi0-f74.google.com with SMTP id u20so3589945oif.1 for ; Mon, 29 Sep 2014 12:37:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pbxcgTYjp5kTSNWTDgCVCwCYWihrDDmeWctiN3MV6M0=; b=HmJvcAIwJCiSn9+eN65+T/aCPFTH+6uS6MUV0BaBcZXVuv+B1uUlOq35v0JC7OsJ01 tcIPjKmJFsfhVYjP+mpIDv82jFOH+LIzml5X/vlpPFqiyKRmBua3MT0fNOp8oQDGNO/4 4ghuYko8HmavXedXx0y0B4cwhPMJGexHYFFaEV9WGIzxgMqu2AGHS/rDpt3hmR1VY+Ui iaqBpKtI2MYMZk0fqLT9ZCg3ALvR/bk4+IvwoLR5txTG7MCfbsZidLt79RlmRIGyO/OR J0SfNz8hGBgbUR9jlaBdiTCvVV5JK2br/HryM8I5L7DIyrJxT4eW8WBQkrwXiJE5DU8z BuBQ== X-Gm-Message-State: ALoCoQkUrnXTEcUJ1Uldyt9GmPRKUmOb+YgQP4DsabAVnsJgkM0yConnLAIPCxsbmtrSs/xdL+L3 X-Received: by 10.182.28.102 with SMTP id a6mr37340871obh.44.1412019446499; Mon, 29 Sep 2014 12:37:26 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id j25si775320yhb.0.2014.09.29.12.37.26 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 29 Sep 2014 12:37:26 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id tBxE4NRB.1; Mon, 29 Sep 2014 12:37:26 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 73376220D90; Mon, 29 Sep 2014 13:37:25 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Mon, 29 Sep 2014 13:34:58 -0600 Message-Id: <1412019326-6721-2-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1412019326-6721-1-git-send-email-sjg@chromium.org> References: <1412019326-6721-1-git-send-email-sjg@chromium.org> Cc: u-boot-review@google.com, Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v3 01/29] sandbox: dts: Add a SPI device and cros_ec device X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add a SPI device which can be used for testing SPI flash features in sandbox. Also add a cros_ec device since with driver model the Chrome OS EC emulation will not otherwise be available. Signed-off-by: Simon Glass --- Changes in v3: None Changes in v2: - Adjust binding to avoid Linux-specific mentions arch/sandbox/dts/sandbox.dts | 26 ++++++++++++++++++++++++++ doc/device-tree-bindings/mtd/spi/spi-flash.txt | 25 +++++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 doc/device-tree-bindings/mtd/spi/spi-flash.txt diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 797478a..7614715 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -1,6 +1,9 @@ /dts-v1/; / { + #address-cells = <1>; + #size-cells = <0>; + chosen { stdout-path = "/serial"; }; @@ -131,4 +134,27 @@ num-gpios = <20>; }; + spi@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + compatible = "sandbox,spi"; + cs-gpios = <0>, <&gpio_a 0>; + flash@0 { + reg = <0>; + compatible = "spansion,m25p16", "sandbox,spi-flash"; + spi-max-frequency = <40000000>; + sandbox,filename = "spi.bin"; + }; + }; + + cros-ec@0 { + compatible = "google,cros-ec"; + #address-cells = <1>; + #size-cells = <1>; + firmware_storage_spi: flash@0 { + reg = <0 0x400000>; + }; + }; + }; diff --git a/doc/device-tree-bindings/mtd/spi/spi-flash.txt b/doc/device-tree-bindings/mtd/spi/spi-flash.txt new file mode 100644 index 0000000..85522d8 --- /dev/null +++ b/doc/device-tree-bindings/mtd/spi/spi-flash.txt @@ -0,0 +1,25 @@ +* MTD SPI driver for serial flash chips + +Required properties: +- #address-cells, #size-cells : Must be present if the device has sub-nodes + representing partitions. +- compatible : Should be the manufacturer and the name of the chip. Bear in + mind that the DT binding is not U-Boot-only, but in case of + U-Boot, see spi_flash_params_table table in + drivers/mtd/spi/sf_params.c for the list of supported chips. +- reg : Chip-Select number +- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at + +Optional properties: + - memory-map : Address and size of the flash, if memory mapped. This may + apply to Intel chipsets, which tend to memory-map flash. + +Example: + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + reg = <0>; + spi-max-frequency = <40000000>; + };