From patchwork Fri Sep 26 11:58:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Khoronzhuk X-Patchwork-Id: 393708 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BCEB4140143 for ; Fri, 26 Sep 2014 21:59:27 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 766784A020; Fri, 26 Sep 2014 13:59:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 06U+FEr11MWY; Fri, 26 Sep 2014 13:59:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A67A84A047; Fri, 26 Sep 2014 13:59:14 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4C24C4A02F for ; Fri, 26 Sep 2014 13:59:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iWATOoXezPBN for ; Fri, 26 Sep 2014 13:58:58 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 17BC44A046 for ; Fri, 26 Sep 2014 13:58:46 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s8QBwjpo029407 for ; Fri, 26 Sep 2014 06:58:45 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8QBwjXG008904 for ; Fri, 26 Sep 2014 06:58:45 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 26 Sep 2014 06:58:44 -0500 Received: from khorivan.synapse.com (incasgf5a_e1_2.itg.ti.com [10.167.216.36]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8QBwHlM005295; Fri, 26 Sep 2014 06:58:43 -0500 From: Ivan Khoronzhuk To: , Date: Fri, 26 Sep 2014 14:58:15 +0300 Message-ID: <1411732695-18070-6-git-send-email-ivan.khoronzhuk@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1411732695-18070-1-git-send-email-ivan.khoronzhuk@ti.com> References: <1411732695-18070-1-git-send-email-ivan.khoronzhuk@ti.com> MIME-Version: 1.0 Cc: w-kwok2@ti.com Subject: [U-Boot] [U-boot] [Patch 5/5] soc: keystone_serdes: generalize configuration mechanism X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The cmu, comlane, lane configuration mechanism are similar for sub systems as well such as PCI or sRIO, but they have different values based on input clock and output bus rate. According to this compact driver to simplify adding different configuration settings based on clock and rate. Signed-off-by: Ivan Khoronzhuk --- drivers/soc/keystone/keystone_serdes.c | 112 +++++++++++++++++++-------------- 1 file changed, 65 insertions(+), 47 deletions(-) diff --git a/drivers/soc/keystone/keystone_serdes.c b/drivers/soc/keystone/keystone_serdes.c index 84ed9ba..dd5eac9 100644 --- a/drivers/soc/keystone/keystone_serdes.c +++ b/drivers/soc/keystone/keystone_serdes.c @@ -29,12 +29,24 @@ #define SERDES_LANE_LOOPBACK BIT(30) #define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10)) +#define SERDES_CMU_CFG_NUM 5 +#define SERDES_COMLANE_CFG_NUM 10 +#define SERDES_LANE_CFG_NUM 10 + struct serdes_cfg { u32 ofs; u32 val; u32 mask; }; +struct cfg_entry { + enum ks2_serdes_clock clk; + enum ks2_serdes_rate rate; + struct serdes_cfg cmu[SERDES_CMU_CFG_NUM]; + struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM]; + struct serdes_cfg lane[SERDES_LANE_CFG_NUM]; +}; + /* SERDES PHY lane enable configuration value, indexed by PHY interface */ static u32 serdes_cfg_lane_enable[] = { 0xf000f0c0, /* SGMII */ @@ -47,39 +59,46 @@ static u32 serdes_cfg_pll_enable[] = { 0xee000000, /* PCSR */ }; -static struct serdes_cfg cfg_cmu_156p25m_5g[] = { - {0x0000, 0x00800000, 0xffff0000}, - {0x0014, 0x00008282, 0x0000ffff}, - {0x0060, 0x00142438, 0x00ffffff}, - {0x0064, 0x00c3c700, 0x00ffff00}, - {0x0078, 0x0000c000, 0x0000ff00} -}; - -static struct serdes_cfg cfg_comlane_156p25m_5g[] = { - {0x0a00, 0x00000800, 0x0000ff00}, - {0x0a08, 0x38a20000, 0xffff0000}, - {0x0a30, 0x008a8a00, 0x00ffff00}, - {0x0a84, 0x00000600, 0x0000ff00}, - {0x0a94, 0x10000000, 0xff000000}, - {0x0aa0, 0x81000000, 0xff000000}, - {0x0abc, 0xff000000, 0xff000000}, - {0x0ac0, 0x0000008b, 0x000000ff}, - {0x0b08, 0x583f0000, 0xffff0000}, - {0x0b0c, 0x0000004e, 0x000000ff} -}; - -static struct serdes_cfg cfg_lane_156p25mhz_5g[] = { - {0x0004, 0x38000080, 0xff0000ff}, - {0x0008, 0x00000000, 0x000000ff}, - {0x000c, 0x02000000, 0xff000000}, - {0x0010, 0x1b000000, 0xff000000}, - {0x0014, 0x00006fb8, 0x0000ffff}, - {0x0018, 0x758000e4, 0xffff00ff}, - {0x00ac, 0x00004400, 0x0000ff00}, - {0x002c, 0x00100800, 0x00ffff00}, - {0x0080, 0x00820082, 0x00ff00ff}, - {0x0084, 0x1d0f0385, 0xffffffff} - +/** + * Array to hold all possible serdes configurations. + * Combination for 5 clock settings and 6 baud rates. + */ +static struct cfg_entry cfgs[] = { + { + .clk = SERDES_CLOCK_156P25M, + .rate = SERDES_RATE_5G, + .cmu = { + {0x0000, 0x00800000, 0xffff0000}, + {0x0014, 0x00008282, 0x0000ffff}, + {0x0060, 0x00142438, 0x00ffffff}, + {0x0064, 0x00c3c700, 0x00ffff00}, + {0x0078, 0x0000c000, 0x0000ff00} + }, + .comlane = { + {0x0a00, 0x00000800, 0x0000ff00}, + {0x0a08, 0x38a20000, 0xffff0000}, + {0x0a30, 0x008a8a00, 0x00ffff00}, + {0x0a84, 0x00000600, 0x0000ff00}, + {0x0a94, 0x10000000, 0xff000000}, + {0x0aa0, 0x81000000, 0xff000000}, + {0x0abc, 0xff000000, 0xff000000}, + {0x0ac0, 0x0000008b, 0x000000ff}, + {0x0b08, 0x583f0000, 0xffff0000}, + {0x0b0c, 0x0000004e, 0x000000ff} + }, + .lane = { + {0x0004, 0x38000080, 0xff0000ff}, + {0x0008, 0x00000000, 0x000000ff}, + {0x000c, 0x02000000, 0xff000000}, + {0x0010, 0x1b000000, 0xff000000}, + {0x0014, 0x00006fb8, 0x0000ffff}, + {0x0018, 0x758000e4, 0xffff00ff}, + {0x00ac, 0x00004400, 0x0000ff00}, + {0x002c, 0x00100800, 0x00ffff00}, + {0x0080, 0x00820082, 0x00ff00ff}, + {0x0084, 0x1d0f0385, 0xffffffff} + }, + }, }; static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask) @@ -105,18 +124,15 @@ static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane, cfg_lane[i].val, cfg_lane[i].mask); } -static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes) +static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes) { u32 i; - ks2_serdes_cfg_setup(base, cfg_cmu_156p25m_5g, - ARRAY_SIZE(cfg_cmu_156p25m_5g)); - ks2_serdes_cfg_setup(base, cfg_comlane_156p25m_5g, - ARRAY_SIZE(cfg_comlane_156p25m_5g)); + ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM); + ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM); for (i = 0; i < num_lanes; i++) - ks2_serdes_lane_config(base, cfg_lane_156p25mhz_5g, - ARRAY_SIZE(cfg_lane_156p25mhz_5g), i); + ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i); return 0; } @@ -173,14 +189,16 @@ int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes) int i; int ret = 0; - /* The driver currently supports 5GBaud rate with ref clock 156.25MHz */ - if (serdes->clk == SERDES_CLOCK_156P25M) - if (serdes->rate == SERDES_RATE_5G) - ret = ks2_serdes_init_156p25m_5g(base, num_lanes); - else - return -EINVAL; - else + for (i = 0; i < ARRAY_SIZE(cfgs); i++) + if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate) + break; + + if (i >= ARRAY_SIZE(cfgs)) { + puts("Cannot find keystone SerDes configuration"); return -EINVAL; + } + + ks2_serdes_init_cfg(base, &cfgs[i], num_lanes); ks2_serdes_cmu_comlane_enable(base, serdes); for (i = 0; i < num_lanes; i++)