From patchwork Thu Sep 25 15:46:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 393375 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5184514017F for ; Fri, 26 Sep 2014 01:47:25 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 26BEF4A02F; Thu, 25 Sep 2014 17:47:23 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id J4dadj-3KDKu; Thu, 25 Sep 2014 17:47:22 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E0434A020; Thu, 25 Sep 2014 17:47:19 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8243A4A020 for ; Thu, 25 Sep 2014 17:47:15 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5Ipm1x6iWaEU for ; Thu, 25 Sep 2014 17:47:13 +0200 (CEST) X-Greylist: delayed 63123 seconds by postgrey-1.27 at theia; Thu, 25 Sep 2014 17:47:08 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1on0115.outbound.protection.outlook.com [157.56.110.115]) by theia.denx.de (Postfix) with ESMTPS id 758B94A01F for ; Thu, 25 Sep 2014 17:47:08 +0200 (CEST) Received: from DM2PR03CA0030.namprd03.prod.outlook.com (10.141.96.29) by BY2PR03MB157.namprd03.prod.outlook.com (10.242.36.12) with Microsoft SMTP Server (TLS) id 15.0.1034.13; Thu, 25 Sep 2014 15:47:04 +0000 Received: from BY2FFO11FD051.protection.gbl (2a01:111:f400:7c0c::115) by DM2PR03CA0030.outlook.office365.com (2a01:111:e400:2428::29) with Microsoft SMTP Server (TLS) id 15.0.1024.12 via Frontend Transport; Thu, 25 Sep 2014 15:47:04 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD051.mail.protection.outlook.com (10.1.15.188) with Microsoft SMTP Server (TLS) id 15.0.1029.15 via Frontend Transport; Thu, 25 Sep 2014 15:47:04 +0000 Received: from oslab-l1.am.freescale.net ([10.214.83.121]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s8PFkx1f014906; Thu, 25 Sep 2014 08:47:02 -0700 From: York Sun To: Date: Thu, 25 Sep 2014 08:46:57 -0700 Message-ID: <1411660018-10010-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(189002)(199003)(97736003)(95666004)(62966002)(90102001)(120916001)(10300001)(83322001)(19580395003)(92566001)(92726001)(99396003)(19580405001)(44976005)(575784001)(6806004)(105606002)(86362001)(106466001)(85852003)(83072002)(68736004)(84676001)(110136001)(85306004)(88136002)(89996001)(87936001)(33646002)(87286001)(104016003)(50226001)(104166001)(4396001)(36756003)(107046002)(2351001)(50986999)(46102003)(80022003)(31966008)(79102003)(81342003)(74662003)(77982003)(81542003)(74502003)(229853001)(102836001)(21056001)(48376002)(50466002)(76482002)(20776003)(64706001)(77156001)(47776003); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR03MB157; H:tx30smr01.am.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR03MB157; X-Forefront-PRVS: 0345CFD558 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=yorksun@freescale.com; X-OriginatorOrg: freescale.com Cc: York Sun , otavio@ossystems.com.br Subject: [U-Boot] [Patch v3, 2/2] board/ls1021aqds: Add DDR4 support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: York Sun --- Chagne log v3: Fix commit message, drop name of ls1021aqds_d4. v2: Drop the name of TARGET_LS1021AQDS_D4 in Kconfig. arch/arm/include/asm/arch-ls102xa/config.h | 5 +++++ board/freescale/ls1021aqds/ddr.c | 9 ++++++++- board/freescale/ls1021aqds/ddr.h | 10 ++++++++++ configs/ls1021aqds_ddr4_nor_defconfig | 3 +++ include/configs/ls1021aqds.h | 4 +++- 5 files changed, 29 insertions(+), 2 deletions(-) create mode 100644 configs/ls1021aqds_ddr4_nor_defconfig diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ed78c33..a500b5b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -50,7 +50,11 @@ #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#else #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 +#endif #define CONFIG_SYS_FSL_DDR #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE @@ -71,6 +75,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #else #error SoC not defined #endif diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 679c654..5898e33 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -79,7 +79,6 @@ found: */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; - popts->cswl_override = DDR_CSWL_CS0; /* * Rtt and Rtt_WR override @@ -89,9 +88,17 @@ found: /* Enable ZQ calibration */ popts->zq_en = 1; +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->cswl_override = DDR_CSWL_CS0; + /* DHC_EN =1, ODT = 75 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } #ifdef CONFIG_SYS_DDR_RAW_TIMING diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h index 16d87cb..f819c99 100644 --- a/board/freescale/ls1021aqds/ddr.h +++ b/board/freescale/ls1021aqds/ddr.h @@ -30,6 +30,13 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,}, + {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, +#elif defined(CONFIG_SYS_FSL_DDR3) {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, @@ -39,6 +46,9 @@ static const struct board_specific_parameters udimm0[] = { {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, +#else +#error DDR type not defined +#endif {} }; diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig new file mode 100644 index 0000000..3c57481 --- /dev/null +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS1021AQDS=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 657e3b6..bb47813 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -49,10 +49,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#define CONFIG_SYS_DDR_RAW_TIMING +#endif #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4