From patchwork Tue Sep 23 14:08:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 392524 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A7EB414007B for ; Wed, 24 Sep 2014 00:08:10 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BBAD5A73F7; Tue, 23 Sep 2014 16:08:07 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vKIPsTVlh+Ip; Tue, 23 Sep 2014 16:08:07 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7ABE4A740E; Tue, 23 Sep 2014 16:07:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D30C5A7401 for ; Tue, 23 Sep 2014 16:07:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X0f4fzUfKMbn for ; Tue, 23 Sep 2014 16:07:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mo4-p04-ob.smtp.rzone.de (mo4-p04-ob.smtp.rzone.de [81.169.146.223]) by theia.denx.de (Postfix) with ESMTPS id D6092A73EA for ; Tue, 23 Sep 2014 16:07:45 +0200 (CEST) X-RZG-CLASS-ID: mo04 X-RZG-AUTH: :IW0NeWC7b/q2i6W/qstXb1SBUuFnrGohfvxEndrDXKjzPMsB3oimjD61I4fPQhgcxQA= Received: from stefan-work.domain_not_set.invalid (b9168f02.cgn.dg-w.de [185.22.143.2]) by post.strato.de (RZmta 35.9 SBL|AUTH) with ESMTPA id R06a9aq8NE7Ular; Tue, 23 Sep 2014 16:07:30 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Tue, 23 Sep 2014 16:08:30 +0200 Message-Id: <1411481312-9929-3-git-send-email-sr@denx.de> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1411481312-9929-1-git-send-email-sr@denx.de> References: <1411481312-9929-1-git-send-email-sr@denx.de> Cc: Marek Vasut , Vince Bridgers , Pavel Machek , Chin Liang See , Dinh Nguyen Subject: [U-Boot] [WIP PATCH 2/4 v2] arm: socfpga: Add Cadence QSPI support to config header X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Cc: Pavel Machek Cc: Michael Trimarchi --- include/configs/socfpga_cyclone5_common.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/include/configs/socfpga_cyclone5_common.h b/include/configs/socfpga_cyclone5_common.h index 3f8f91f..d183510 100644 --- a/include/configs/socfpga_cyclone5_common.h +++ b/include/configs/socfpga_cyclone5_common.h @@ -142,6 +142,37 @@ #endif /* + * QSPI support + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_CADENCE_QSPI +#define CONFIG_CQSPI_BASE (SOCFPGA_QSPI_ADDRESS) +#define CONFIG_CQSPI_AHB_BASE (SOCFPGA_QSPIDATA_ADDRESS) +#define CONFIG_SPI_FLASH /* SPI flash subsystem */ +#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ +#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ +#define CONFIG_SPI_FLASH_MTD +/* Flash device info */ +#define CONFIG_SF_DEFAULT_SPEED (50000000) +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_QUAD (1) +/* QSPI reference clock */ +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif +/* QSPI page size and block size */ +#define CONFIG_CQSPI_PAGE_SIZE (256) +#define CONFIG_CQSPI_BLOCK_SIZE (16) +/* QSPI Delay timing */ +#define CONFIG_CQSPI_TSHSL_NS (200) +#define CONFIG_CQSPI_TSD2D_NS (255) +#define CONFIG_CQSPI_TCHSH_NS (20) +#define CONFIG_CQSPI_TSLCH_NS (20) +#define CONFIG_CQSPI_DECODER (0) +#endif /* CONFIG_CMD_SF */ + +/* * Serial Driver */ #define CONFIG_SYS_NS16550