From patchwork Wed Sep 17 08:03:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Baldyga X-Patchwork-Id: 390307 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 79B96140111 for ; Wed, 17 Sep 2014 18:04:44 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E3878A74B9; Wed, 17 Sep 2014 10:04:37 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LZsWcbpCLvS1; Wed, 17 Sep 2014 10:04:37 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E3F1BA74A7; Wed, 17 Sep 2014 10:04:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B1EE9A748C for ; Wed, 17 Sep 2014 10:04:34 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id srBXQGDto3-j for ; Wed, 17 Sep 2014 10:04:33 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by theia.denx.de (Postfix) with ESMTPS id 3F769A74A7 for ; Wed, 17 Sep 2014 10:04:21 +0200 (CEST) Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NC1000TDD36N330@mailout1.samsung.com> for u-boot@lists.denx.de; Wed, 17 Sep 2014 17:04:18 +0900 (KST) X-AuditID: cbfee61b-f79f86d00000144c-c6-541940825c5c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 45.EE.05196.28049145; Wed, 17 Sep 2014 17:04:18 +0900 (KST) Received: from AMDC2122.DIGITAL.local ([106.120.53.17]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NC100JH1D25G520@mmp1.samsung.com>; Wed, 17 Sep 2014 17:04:18 +0900 (KST) From: Robert Baldyga To: u-boot@lists.denx.de, mk7.kang@samsung.com Date: Wed, 17 Sep 2014 10:03:36 +0200 Message-id: <1410941017-15499-3-git-send-email-r.baldyga@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1410941017-15499-1-git-send-email-r.baldyga@samsung.com> References: <1410941017-15499-1-git-send-email-r.baldyga@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFJMWRmVeSWpSXmKPExsVy+t9jAd0mB8kQgyk3tSzePNzMaNFxpIXR YsflGywWDw7vZLd4u7eT3YHV4+ydHYwefVtWMQYwRXHZpKTmZJalFunbJXBlvG8RKTgqUnHv 5BLWBsavAl2MnBwSAiYSU6Z+YoewxSQu3FvPBmILCSxilPh0WbOLkQvIbmeS+DF7IViCTUBH Ysv3CYwgtoiAnsS8Se/A4swC0RKdmxuZQWxhASuJCT92g8VZBFQl7m++xARi8wq4SlzacpcR YpmcxMljk1lBbE4BN4mf07+xQix2lZg86SDjBEbeBYwMqxhFUwuSC4qT0nON9IoTc4tL89L1 kvNzNzGCQ+SZ9A7GVQ0WhxgFOBiVeHg3XJYIEWJNLCuuzD3EKMHBrCTC22MhGSLEm5JYWZVa lB9fVJqTWnyIUZqDRUmc92CrdaCQQHpiSWp2ampBahFMlomDU6qBkaX3daLDgZ6Axw0lve9m blRR2mPL1rjpdk7FPOFlPmZ/vO5qPuu8snk+w7elr5wW7J1f+LEjeDd71+IjNq67nwWLbNWc sGWqzlrdHr8JL5WY9Nwvel9Ytl/xz5rujnmul4o+LjqkoKvq+K5X7cqJlap6crZ8Pp+b+qV2 G27b5qRWYHODY195qRJLcUaioRZzUXEiACpPlC4NAgAA Cc: p.marczak@samsung.com Subject: [U-Boot] [PATCH 2/3] arm: goni: update SDRAM memory layout X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de According to changes in memory configuration in first stage bootloader, we change PHYS_SDRAM_1 from 0x30000000 to 0x20000000. This change revealed problem in memory handling at goni platform, so this patch fix this problem by changing CONFIG_SYS_SDRAM_BASE to 0x40000000. So far SDRAM base was set to 0x30000000 and total memory size was calulated as sum of memory sizes in all banks. But at goni platform memory address range is not continuous. We have: 0x20000000-0x24ffffff - 80 MiB 0x25000000-0x3fffffff - gap 0x40000000-0x4fffffff - 256 MiB 0x50000000-0x57ffffff - 128 MiB It caused problem - u-boot has seen memory area as continous, so it could try to read/write to memory address in the gap range. The solution would be to create algorithm of handling non-continous memory area, but it's much simpler to omit the first memory range and gap between 0x25000000-0x3fffffff, and set memory base to 0x40000000. It decreases total available memory size from 464 MiB to 384 MiB, but after all we have still more than enough memory for each u-boot feature. Signed-off-by: Robert Baldyga --- board/samsung/goni/goni.c | 3 +-- include/configs/s5p_goni.h | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index eb0f9bf..9aceb2e 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -50,8 +50,7 @@ int power_init_board(void) int dram_init(void) { - gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + - PHYS_SDRAM_3_SIZE; + gd->ram_size = PHYS_SDRAM_2_SIZE + PHYS_SDRAM_3_SIZE; return 0; } diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 82bd212..eab9288 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -29,10 +29,10 @@ #define CONFIG_SYS_CLK_FREQ_C110 24000000 /* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CONFIG_SYS_SDRAM_BASE 0x40000000 /* Text Base */ -#define CONFIG_SYS_TEXT_BASE 0x34800000 +#define CONFIG_SYS_TEXT_BASE 0x41800000 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG @@ -220,7 +220,7 @@ /* Goni has 3 banks of DRAM, but swap the bank */ #define CONFIG_NR_DRAM_BANKS 3 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ +#define PHYS_SDRAM_1 0x20000000 /* OneDRAM Bank #0 */ #define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ #define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ #define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */