From patchwork Mon Sep 15 11:59:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 389298 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D5940140082 for ; Mon, 15 Sep 2014 21:59:47 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2A3CFA73FE; Mon, 15 Sep 2014 13:59:46 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id di-M5w9708Td; Mon, 15 Sep 2014 13:59:45 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DBF7FA76F5; Mon, 15 Sep 2014 13:59:43 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 629CEA78FF for ; Mon, 15 Sep 2014 13:59:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8yrqfGRqcyoE for ; Mon, 15 Sep 2014 13:59:36 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9]) by theia.denx.de (Postfix) with ESMTPS id 609D9A76F5 for ; Mon, 15 Sep 2014 13:59:32 +0200 (CEST) Received: from mail.nefkom.net (unknown [192.168.8.184]) by mail-out.m-online.net (Postfix) with ESMTP id 3hxR2C4tttz3hj72; Mon, 15 Sep 2014 13:59:31 +0200 (CEST) X-Auth-Info: gwHO5c179U1NTwdLgS1ipBjvOxWMwmgcf+1agCFXSBU= Received: from chi.lan (unknown [195.140.253.167]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3hxR2C0k1gzvdWV; Mon, 15 Sep 2014 13:59:30 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 15 Sep 2014 13:59:25 +0200 Message-Id: <1410782365-7239-1-git-send-email-marex@denx.de> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1410779188-6880-1-git-send-email-marex@denx.de> References: <1410779188-6880-1-git-send-email-marex@denx.de> Cc: Marek Vasut , Pavel Machek , Chin Liang See , Tom Rini Subject: [U-Boot] [PATCH 30/35] arm: socfpga: cache: Enable D-Cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- board/altera/socfpga/socfpga_cyclone5.c | 1 + include/configs/socfpga_cyclone5.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 4149842..6b98277 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -35,6 +35,7 @@ int board_early_init_f(void) int board_init(void) { icache_enable(); + dcache_enable(); /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index f0eac4d..20da1ac 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -18,7 +18,6 @@ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 -#define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ #define CONFIG_MISC_INIT_R @@ -26,6 +25,7 @@ #define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 /* base address for .text section */