From patchwork Sun Sep 14 22:29:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 389159 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4A7FA14007D for ; Mon, 15 Sep 2014 08:32:27 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A4AB9A7433; Mon, 15 Sep 2014 00:31:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id exD0ty+G7YvP; Mon, 15 Sep 2014 00:31:47 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DB8ACA7A61; Mon, 15 Sep 2014 00:30:39 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DA3B1A77F4 for ; Mon, 15 Sep 2014 00:30:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id I48n9aszkGl3 for ; Mon, 15 Sep 2014 00:30:08 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qg0-f74.google.com (mail-qg0-f74.google.com [209.85.192.74]) by theia.denx.de (Postfix) with ESMTPS id 07DA8A7A2E for ; Mon, 15 Sep 2014 00:29:44 +0200 (CEST) Received: by mail-qg0-f74.google.com with SMTP id q107so310705qgd.5 for ; Sun, 14 Sep 2014 15:29:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bFLctIq4O3alVKgrBXYnIQWQeOLelHbOthOmbcfSkIU=; b=N7ux52MDYwi9UMz9FwTDe/sSArnsgFCgtlWBIaQH5D1VIE+ynaOS9AJO7tvkBTxrzN ceXCdw9Pmd9ySOEeXFaE8y4omL05m61HvWQl0kYepaE4JiHaXS0r+2AuSC5tC4LX+II1 PZ7AEjyRmh8N5BxMQv0rXpdGQQBZrx5l2A11SEa7+pYcoXP3cFOTn+DNGa3W5Ez8rSRw fXKgEFGH/dnOFblm/AZDjbkEMDzSwk2AG7b1OO+BhHsfuvT+1Jy2njteHbVxuNYbBIFk Z4KEBboyC6mU4hLJvh+Qim/oClTxS9FqXsV9gKkN6giFcpHIELqW1X1MwVIGtFJjPKeX VnCg== X-Gm-Message-State: ALoCoQlEKaNfpDY69R1Xunn2jEiNK/GyrDJRbaDK8lO6uF63j9psirmqKUD748mcqmNIK0p5e0vj X-Received: by 10.224.173.2 with SMTP id n2mr12785584qaz.6.1410733782975; Sun, 14 Sep 2014 15:29:42 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id e24si463160yhe.3.2014.09.14.15.29.42 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 14 Sep 2014 15:29:42 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id MkSBoGeg.1; Sun, 14 Sep 2014 15:29:42 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id D96C9221EA7; Sun, 14 Sep 2014 16:29:41 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Sun, 14 Sep 2014 16:29:24 -0600 Message-Id: <1410733771-5182-6-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1410733771-5182-1-git-send-email-sjg@chromium.org> References: <1410733771-5182-1-git-send-email-sjg@chromium.org> Cc: u-boot-review@google.com, Tom Warren Subject: [U-Boot] [PATCH v8 05/12] dm: exynos: Add pinctrl settings for smdkc100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: Simon Glass --- Changes in v8: - Add patch containing pinctrl settings for s5p_goni Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None arch/arm/dts/s5pc100-pinctrl.dtsi | 180 ++++++++++++++++++++++++++++++++++++++ arch/arm/dts/s5pc1xx-smdkc100.dts | 7 ++ 2 files changed, 187 insertions(+) create mode 100644 arch/arm/dts/s5pc100-pinctrl.dtsi diff --git a/arch/arm/dts/s5pc100-pinctrl.dtsi b/arch/arm/dts/s5pc100-pinctrl.dtsi new file mode 100644 index 0000000..bd9f97c --- /dev/null +++ b/arch/arm/dts/s5pc100-pinctrl.dtsi @@ -0,0 +1,180 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/ { + pinctrl@e0300000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc: gpc { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd: gpd { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpi: gpi { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj3: gpj3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl3: gpl3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl4: gpl4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph2: gph2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph3: gph3 { + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts index 42754ce..95f15ed 100644 --- a/arch/arm/dts/s5pc1xx-smdkc100.dts +++ b/arch/arm/dts/s5pc1xx-smdkc100.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "skeleton.dtsi" +#include "s5pc100-pinctrl.dtsi" / { model = "Samsung SMDKC100 based on S5PC100"; @@ -17,6 +18,12 @@ aliases { serial0 = "/serial@ec000000"; console = "/serial@ec000000"; + pinctrl0 = &pinctrl0; + }; + + pinctrl0: pinctrl@e0300000 { + compatible = "samsung,s5pc100-pinctrl"; + reg = <0xe0200000 0x1000>; }; serial@ec000000 {