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[U-Boot,U-boot,3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC

Message ID 1409765724-1180-4-git-send-email-ivan.khoronzhuk@ti.com
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

Ivan Khoronzhuk Sept. 3, 2014, 5:35 p.m. UTC 
From: Hao Zhang <hzhang@ti.com>

This patch adds Keystone II Lamar (K2L) SoC specific definitions
to support MSMC cache coherency.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
---
 arch/arm/cpu/armv7/keystone/init.c | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index a8f8aee..a0ecfa2 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -32,6 +32,9 @@  int arch_cpu_init(void)
 #ifdef CONFIG_SOC_K2E
 	msmc_share_all_segments(13); /* PCIE 1 */
 #endif
+#ifdef CONFIG_SOC_K2L
+	msmc_share_all_segments(14); /* PCIE 1 */
+#endif
 
 	/*
 	 * just initialise the COM2 port so that TI specific