From patchwork Wed Aug 27 20:29:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnab Basu X-Patchwork-Id: 383559 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 933611400A0 for ; Thu, 28 Aug 2014 06:31:51 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7B8F5A755D; Wed, 27 Aug 2014 22:31:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id z5gDkw41-SsL; Wed, 27 Aug 2014 22:31:47 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B6178A756C; Wed, 27 Aug 2014 22:31:32 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5BA42A7550 for ; Wed, 27 Aug 2014 22:31:29 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id V+439WZRy2qe for ; Wed, 27 Aug 2014 22:31:26 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1lp0145.outbound.protection.outlook.com [207.46.163.145]) by theia.denx.de (Postfix) with ESMTPS id 29AB9A754E for ; Wed, 27 Aug 2014 22:31:23 +0200 (CEST) Received: from CH1PR03CA001.namprd03.prod.outlook.com (10.255.156.146) by BN1PR0301MB0738.namprd03.prod.outlook.com (25.160.78.145) with Microsoft SMTP Server (TLS) id 15.0.1015.19; Wed, 27 Aug 2014 20:31:20 +0000 Received: from BN1AFFO11FD035.protection.gbl (10.255.156.132) by CH1PR03CA001.outlook.office365.com (10.255.156.146) with Microsoft SMTP Server (TLS) id 15.0.1015.19 via Frontend Transport; Wed, 27 Aug 2014 20:31:19 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD035.mail.protection.outlook.com (10.58.52.159) with Microsoft SMTP Server (TLS) id 15.0.1010.11 via Frontend Transport; Wed, 27 Aug 2014 20:31:19 +0000 Received: from lvd5228.zin33.ap.freescale.net (lvd5228.ap.freescale.net [10.232.32.228]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s7RKUJQv012409; Wed, 27 Aug 2014 13:31:16 -0700 From: Arnab Basu To: , , , Date: Thu, 28 Aug 2014 01:59:58 +0530 Message-ID: <1409171401-22616-6-git-send-email-arnab.basu@freescale.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1409171401-22616-1-git-send-email-arnab.basu@freescale.com> References: <1409171401-22616-1-git-send-email-arnab.basu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(199003)(189002)(33646002)(102836001)(575784001)(26826002)(83072002)(50226001)(85306004)(4396001)(31966008)(90102001)(106466001)(104016003)(2201001)(46102001)(104166001)(21056001)(76482001)(50466002)(86362001)(97736001)(6806004)(105606002)(87936001)(88136002)(77982001)(74662001)(95666004)(74502001)(76176999)(48376002)(77156001)(20776003)(19580405001)(99396002)(44976005)(19580395003)(50986999)(64706001)(229853001)(93916002)(85852003)(81342001)(36756003)(92726001)(107046002)(79102001)(92566001)(68736004)(89996001)(80022001)(47776003)(87286001)(84676001)(81542001)(83322001)(62966002)(41533002); DIR:OUT; SFP:; SCL:1; SRVR:BN1PR0301MB0738; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 0316567485 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=arnab.basu@freescale.com; X-OriginatorOrg: freescale.com Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 5/8] ARMv8: PCSI: Add generic ARMv8 PSCI code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). This is largely ported from the similar code that exists for ARMv7 Signed-off-by: Arnab Basu Reviewed-by: Bhupesh Sharma Cc: Marc Zyngier --- arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/psci.S | 171 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 172 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv8/psci.S diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 4f0ea87..8f6988d 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -15,3 +15,4 @@ obj-y += cache.o obj-y += tlb.o obj-y += transition.o obj-y += cpu-dt.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S new file mode 100644 index 0000000..5f4e3b2 --- /dev/null +++ b/arch/arm/cpu/armv8/psci.S @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2014 + * Arnab Basu + * + * Based on arch/arm/cpu/armv7/psci.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +.pushsection ._secure.text, "ax" + +ENTRY(psci_0_2_cpu_suspend_64) +ENTRY(psci_0_2_cpu_on_64) +ENTRY(psci_0_2_affinity_info_64) +ENTRY(psci_0_2_migrate_64) +ENTRY(psci_0_2_migrate_info_up_cpu_64) + mov x0, #ARM_PSCI_RET_NI /* Return -1 (Not Implemented) */ + ret +ENDPROC(psci_0_2_cpu_suspend_64) +ENDPROC(psci_0_2_cpu_on_64) +ENDPROC(psci_0_2_affinity_info_64) +ENDPROC(psci_0_2_migrate_64) +ENDPROC(psci_0_2_migrate_info_up_cpu_64) +.weak psci_0_2_cpu_suspend_64 +.weak psci_0_2_cpu_on_64 +.weak psci_0_2_affinity_info_64 +.weak psci_0_2_migrate_64 +.weak psci_0_2_migrate_info_up_cpu_64 + +ENTRY(psci_0_2_psci_version) + mov x0, #2 /* Return Major = 0, Minor = 2*/ + ret +ENDPROC(psci_0_2_psci_version) + +.align 4 +_psci_0_2_table: + .quad PSCI_0_2_FN_PSCI_VERSION + .quad psci_0_2_psci_version + .quad PSCI_0_2_FN64_CPU_SUSPEND + .quad psci_0_2_cpu_suspend_64 + .quad PSCI_0_2_FN64_CPU_ON + .quad psci_0_2_cpu_on_64 + .quad PSCI_0_2_FN64_AFFINITY_INFO + .quad psci_0_2_affinity_info_64 + .quad PSCI_0_2_FN64_MIGRATE + .quad psci_0_2_migrate_64 + .quad PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU + .quad psci_0_2_migrate_info_up_cpu_64 + .quad 0 + .quad 0 + +.macro psci_enter + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + stp x17, x18, [sp, #-16]! + stp x15, x16, [sp, #-16]! + stp x13, x14, [sp, #-16]! + stp x11, x12, [sp, #-16]! + stp x9, x10, [sp, #-16]! + stp x7, x8, [sp, #-16]! + stp x5, x6, [sp, #-16]! + mrs x5, elr_el3 + stp x5, x4, [sp, #-16]! + + /* EL0 and El1 will execute in secure */ + mrs x4, scr_el3 + bic x4, x4, #1 + msr scr_el3, x4 +.endm + +.macro psci_return + /* EL0 and El1 will execute in non-secure */ + mrs x4, scr_el3 + orr x4, x4, #1 + msr scr_el3, x4 + + ldp x5, x4, [sp], #16 + msr elr_el3, x5 + ldp x5, x6, [sp], #16 + ldp x7, x8, [sp], #16 + ldp x9, x10, [sp], #16 + ldp x11, x12, [sp], #16 + ldp x13, x14, [sp], #16 + ldp x15, x16, [sp], #16 + ldp x17, x18, [sp], #16 + ldp x19, x20, [sp], #16 + ldp x21, x22, [sp], #16 + ldp x23, x24, [sp], #16 + ldp x25, x26, [sp], #16 + ldp x27, x28, [sp], #16 + ldp x29, x30, [sp], #16 + eret +.endm + +ENTRY(_smc_psci) + psci_enter + adr x4, _psci_0_2_table +1: ldr x5, [x4] /* Load PSCI function ID */ + ldr x6, [x4, #8] /* Load target PC */ + cmp x5, #0 /* If reach the end, bail out */ + b.eq fn_not_found + cmp x0, x5 /* If not matching, try next entry */ + b.eq fn_call + add x4, x4, #16 + b 1b + +fn_call: + blr x6 + psci_return + +fn_not_found: + mov x0, #ARM_PSCI_RET_INVAL /* Return -2 (Invalid) */ + psci_return +ENDPROC(_smc_psci) + +ENTRY(default_psci_vector) + eret +ENDPROC(default_psci_vector) + +.align 2 +__handle_sync: + str x4, [sp, #-8]! + mrs x4, esr_el3 + ubfx x4, x4, #26, #6 + cmp x4, #0x17 + b.eq smc_found + ldr x4, [sp], #8 + b default_psci_vector +smc_found: + ldr x4, [sp], #8 + b _smc_psci + +/* + * PSCI Exception vectors. + */ + .align 11 + .globl psci_vectors +psci_vectors: + .align 7 + b default_psci_vector /* Current EL Synchronous Thread */ + .align 7 + b default_psci_vector /* Current EL IRQ Thread */ + .align 7 + b default_psci_vector /* Current EL FIQ Thread */ + .align 7 + b default_psci_vector /* Current EL Error Thread */ + .align 7 + b default_psci_vector /* Current EL Synchronous Handler */ + .align 7 + b default_psci_vector /* Current EL IRQ Handler */ + .align 7 + b default_psci_vector /* Current EL FIQ Handler */ + .align 7 + b default_psci_vector /* Current EL Error Handler */ + .align 7 + b __handle_sync /* Lower EL Synchronous (64b) */ + .align 7 + b default_psci_vector /* Lower EL IRQ (64b) */ + .align 7 + b default_psci_vector /* Lower EL FIQ (64b) */ + .align 7 + b default_psci_vector /* Lower EL Error (64b) */ + +.popsection