From patchwork Tue Aug 26 15:34:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 383156 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 13C341400D7 for ; Wed, 27 Aug 2014 01:41:23 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 715D3A7412; Tue, 26 Aug 2014 17:40:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3jRvtb-cTY9k; Tue, 26 Aug 2014 17:40:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BF949A74DA; Tue, 26 Aug 2014 17:37:22 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C17B5A7449 for ; Tue, 26 Aug 2014 17:37:07 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6f6vyMe5xHZc for ; Tue, 26 Aug 2014 17:37:04 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by theia.denx.de (Postfix) with ESMTPS id 65B1DA745A for ; Tue, 26 Aug 2014 17:35:31 +0200 (CEST) Received: by mail-wi0-f177.google.com with SMTP id ho1so4367743wib.16 for ; Tue, 26 Aug 2014 08:35:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qw5m9DZ5gyyy2B7oP4OB/aVxgvXcO433WnAeTgSQguI=; b=hm6Njk99elAJhb5bQLQDih9EXdszO5vwbIhc+K3ADzDeAZknZfnkQfi7VGeKXh/72H ei+tIlB0+TzeWM8ogZK6aIGJ34TkChYYPRiLNd2p88Ex5/UW6l2jzOs39GKc7IfTW5CY GHmIiw9meEnAQtYcUlnaNI8/R6ic8PAatnaSKIvmRFuiN1c+loNLbBVz0qgwCPTIjJ8t 3Pa5VBXk0VINskF0UsacoU3DfOXx/9XMJYQawXIezQMa9ByoAa4SYcsiDT9KaLLPc5+9 mcQZeK84cvkKugkyYfocHmW62hA2dXZS3Y9Wkf8SqTiLt1O9ImABcxhDKZB7e7exmdNh jr/w== X-Received: by 10.180.89.100 with SMTP id bn4mr23068209wib.34.1409067331635; Tue, 26 Aug 2014 08:35:31 -0700 (PDT) Received: from localhost (port-7111.pppoe.wtnet.de. [84.46.27.226]) by mx.google.com with ESMTPSA id w10sm3562702wix.10.2014.08.26.08.35.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Aug 2014 08:35:31 -0700 (PDT) From: Thierry Reding To: Tom Warren , Simon Glass Date: Tue, 26 Aug 2014 17:34:20 +0200 Message-Id: <1409067268-956-33-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.0.4 In-Reply-To: <1409067268-956-1-git-send-email-thierry.reding@gmail.com> References: <1409067268-956-1-git-send-email-thierry.reding@gmail.com> Cc: u-boot@lists.denx.de, Stephen Warren Subject: [U-Boot] [PATCH v2 32/40] ARM: cache_v7: Various minor cleanups X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Thierry Reding Remove two gratuituous blank lines, uses u32 (instead of int) as the type for values that will be written to a register, moves the beginning of the variable declaration section to a separate line (rather than the one with the opening brace) and keeps the function signature on a single line where possible. Signed-off-by: Thierry Reding Acked-by: Simon Glass --- arch/arm/cpu/armv7/cache_v7.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a2c4032fed8c..0f9d8377ed5a 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -21,7 +21,8 @@ * to get size details from Current Cache Size ID Register(CCSIDR) */ static void set_csselr(u32 level, u32 type) -{ u32 csselr = level << 1 | type; +{ + u32 csselr = level << 1 | type; /* Write to Cache Size Selection Register(CSSELR) */ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); @@ -49,7 +50,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -73,7 +75,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -134,7 +137,6 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation) static void v7_maint_dcache_all(u32 operation) { u32 level, cache_type, level_start_bit = 0; - u32 clidr = get_clidr(); for (level = 0; level < 7; level++) { @@ -147,8 +149,7 @@ static void v7_maint_dcache_all(u32 operation) } } -static void v7_dcache_clean_inval_range(u32 start, - u32 stop, u32 line_len) +static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) { u32 mva; @@ -256,7 +257,6 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop);